loaded into the m unit is usually called a synchr as includesa 16-bitregister that can be used to store data from the processor,this register might be connected to a set of LEDs to allow display of data on the DE2 board.To allow eoo心ec8 ne peraon the ceum心 he addr lines conected to the memory:for this xerisea memory with 128words is probably sufficient,which implies 目 Processor Memory ADDR DOU DIN Clock Resetn Run -LEDS Figure 8.Connecting the enhanced processor to a memory and output register. 1.Create a new Quartus II project for the enhanced version of the processor. 2.Write VHDL code for the processor and test your circuit by using functional simulation:apply instructions to the DIN port and observe the intemal processor signals as the instructions are executed.Pay careful memory has register 3 Create Follow the instructions provided by the wizard to create a memory that has one 16-bit wide read/write data port and is 128 words deep.Use a MIF file to store instructions in the memory that are to be executed by your processo 5.Include in your proiect the necessary pin assignments to implement your circuit on the DE2 board.Use switch SW to drive the processor'sm input,use Resem,and use the board's 50 MHz clock signal as the Clock nput Since the circu t needs to r prope sure that a timing iru a mify your VHDL loaded into the memory on an active clock edge. This type of memory unit is usually called a synchronous random access memory (synchronous RAM). Figure 8 also includes a 16-bit register that can be used to store data from the processor; this register might be connected to a set of LEDs to allow display of data on the DE2 board. To allow the processor to select either the memory unit or register when performing a write operation, the circuit includes some logic gates that perform address decoding: if the upper address lines are A 15A14A13A12 = 0000, then the memory module will be written at the address given on the lower address lines. Figure 8 shows n lower address lines connected to the memory; for this exercise a memory with 128 words is probably sufficient, which implies that n = 7 and the memory address port is driven by A6 ...A0. For addresses in which A15A14A13A12 = 0001, the data written by the processor is loaded into the register whose outputs are called LEDs in Figure 8. Resetn Clock Memory 16 addr q Processor 16 DIN ADDR Resetn RunDone Run 16 DOUT wr_en data A15 } A12 n W A15 } A12 4 4 16 E D Q LEDs Figure 8. Connecting the enhanced processor to a memory and output register. 1. Create a new Quartus II project for the enhanced version of the processor. 2. Write VHDL code for the processor and test your circuit by using functional simulation: apply instructions to the DIN port and observe the internal processor signals as the instructions are executed. Pay careful attention to the timing of signals between your processor and external memory; account for the fact that the memory has registered input ports, as we discussed for Figure 8. 3. Create another Quartus II project that instantiates the processor, memory module, and register shown in Fig￾ure 8. Use the Quartus II MegaWizard Plug-In Manager tool to create the ALTSYNCRAM memory module. Follow the instructions provided by the wizard to create a memory that has one 16-bit wide read/write data port and is 128 words deep. Use a MIF file to store instructions in the memory that are to be executed by your processor. 4. Use functional simulation to test the circuit. Ensure that data is read properly from the RAM and executed by the processor. 5. Include in your project the necessary pin assignments to implement your circuit on the DE2 board. Use switch SW17 to drive the processor’s Run input, use KEY0 for Resetn, and use the board’s 50 MHz clock signal as the Clock input. Since the circuit needs to run properly at 50 MHz, make sure that a timing constraint is set in Quartus II to constrain the circuit’s clock to this frequency. Read the Report produced by the Quartus II Timing Analyzer to ensure that your circuit operates at this speed; if not, use the Quartus II tools to analyze your circuit and modify your VHDL code to make a more efficient design that meets the 3