研究生课程教学大纲 the devices and models in integrated circuits,to grasp the layout matching,and to design the interconnection,and to consider the design of ESD protection. Chapter4 Gate engineering in nano CMOS devices(hours:6) (1)MIS gate structure in CMOS devices (Ih) (2)Silicon oxynitride gate dielectric (Ih) (3)High dielectric constant gate dielectric (3h) (4)New gate electrode materials in nano CMOS technology (Ih) This chapter includes the gate engineering of CMOS device,describes the characteristics of high dielectric constant gate dielectric MOSFET and FIBL effects.Through the study of this chapter,students are required to master the FIBL effects,design considerations of high dielectric constant gate dielectric devices and gate capacitance calculation of nanoscale MOSFET's Chapter5 Channel engineering and ultra shallow junction technology of nano CMOS devices(hours:6) (1)Problems to be solved in channel engineering (0.5h) (2)Vertical channel engineering (2h) (3)Horizontal channel engineering in nano CMOS devices (3h) (4)Development of ultra shallow junction and related ion doping in nano CMOS (0.5h) Through the study of this chapter,students are required to understand principle of non-uniform doping,and master the design and optimization of the transverse and longitudinal channel engineering Chapter6 Novel nano CMOS devices hours:6) (1)Novel substrate structure device (2h) (2)New gate structure device (2h) (3)New channel structure device (Ih) (4)Junctionless MOS transistor (Ih) This chapter explains the performance analysis of SOI MOSFET,working principle of FinFET,and strain silicon technology.Through the study of this chapter,students are required to master threshold voltage and subthreshold slope of SOI MOSFET,working principle of FinFET,研究生课程教学大纲 7 the devices and models in integrated circuits, to grasp the layout matching, and to design the interconnection, and to consider the design of ESD protection. Chapter4 Gate engineering in nano CMOS devices( hours: 6 ) (1) MIS gate structure in CMOS devices（1h） (2) Silicon oxynitride gate dielectric（1h） (3) High dielectric constant gate dielectric（3h） (4) New gate electrode materials in nano CMOS technology（1h） This chapter includes the gate engineering of CMOS device , describes the characteristics of high dielectric constant gate dielectric MOSFET and FIBL effects. Through the study of this chapter, students are required to master the FIBL effects, design considerations of high dielectric constant gate dielectric devices and gate capacitance calculation of nanoscale MOSFET’s. Chapter5 Channel engineering and ultra shallow junction technology of nano CMOS devices( hours: 6 ) (1) Problems to be solved in channel engineering（0.5h） (2) Vertical channel engineering（2h） (3) Horizontal channel engineering in nano CMOS devices（3h） (4) Development of ultra shallow junction and related ion doping in nano CMOS（0.5h） Through the study of this chapter, students are required to understand principle of non-uniform doping, and master the design and optimization of the transverse and longitudinal channel engineering. Chapter6 Novel nano CMOS devices ( hours: 6 ) (1) Novel substrate structure device（2h） (2) New gate structure device（2h） (3) New channel structure device（1h） (4) Junctionless MOS transistor（1h） This chapter explains the performance analysis of SOI MOSFET, working principle of FinFET, and strain silicon technology. Through the study of this chapter, students are required to master threshold voltage and subthreshold slope of SOI MOSFET ,working principle of FinFET