电子科学与工程学院2020-2021学年 研究生课程教学大纲目录 03015001《集成电子学》教学大纲… 03015001 Syllabus of Integrated Electronics
电子科学与工程学院 2020-2021 学年 研究生课程教学大纲目录 03015001《集成电子学》教学大纲............................................................................................. 1 03015001 Syllabus of Integrated Electronics..................................................................................5
研究生课程教学大纲 课程代码《课程名称》教学大纲 课程 课程中 03015001 集成电子学 学时 50 编号 文名称 ☑学位课 课程 课程英 口非学位课 Integrated Electronics 性质 2.5 文名称 学分 口其他 开课 ☑春 适用学科 适用 ☑硕士 微电子学与固体电子学 时间口秋 (类别) 学生 口博士 先修课程 半导体物理、微电子器件、半导体集成电路、微电子工艺技术 开课单位 电子科学与工程学院 大纲撰写人 陈勇 大纲审稿人 制(修)定时间 一、教学目标 《集成电子学》课程主要讲述集成电路的核心基础问题。通过本课程教学,使学生了解 集成电路的发展动态和技术趋势,掌握超大规模集成物理、纳米CMOS集成电路所面临的 挑战和工程技术解决手段,以及新型COS器件和集成技术,具备研发集成电路的必备核 心知识和扎实的基础。 二、教学内容与要求 第一章:超大规模集成导论(4学时) 1本章教学内容: (1)集成电路的发展(0.5学时) (2)神奇的摩尔定律(0.5学时) (3)不同时期半导体技术所使用的材料(0.5学时) (4)集成电路制造工艺流程(0学时) (5)按比例缩小定律(1.5学时) (6)微电子技术的发展方向(1学时) 2本章教学要求:通过本章课程的学习,要求学生理解集成电路发展动态和趋势,掌握 集成电路中的材料及按比例缩小。 3本章教学重点:理解摩尔定律以及按比例缩小定律。 4本章教学难点:CE率及CV率尺寸缩小前后的性能比较。 第二章:缩小到纳米尺寸的CM0S器件面临的挑战(12学时)
研究生课程教学大纲 1 课程代码《课程名称》教学大纲 课程 编号 03015001 课程中 文名称 集成电子学 学时 50 课程 性质 学位课 □非学位课 □其他 课程英 文名称 Integrated Electronics 学分 2.5 开课 时间 春 □秋 适用学科 (类别) 微电子学与固体电子学 适用 学生 硕士 □博士 先修课程 半导体物理、微电子器件、半导体集成电路、微电子工艺技术 开课单位 电子科学与工程学院 大纲撰写人 陈勇 大纲审稿人 制(修)定时间 一、教学目标 《集成电子学》课程主要讲述集成电路的核心基础问题。通过本课程教学,使学生了解 集成电路的发展动态和技术趋势,掌握超大规模集成物理、纳米 CMOS 集成电路所面临的 挑战和工程技术解决手段,以及新型 CMOS 器件和集成技术,具备研发集成电路的必备核 心知识和扎实的基础。 二、教学内容与要求 第一章:超大规模集成导论(4 学时) 1 本章教学内容: (1) 集成电路的发展(0.5 学时) (2) 神奇的摩尔定律(0.5 学时) (3) 不同时期半导体技术所使用的材料(0.5 学时) (4) 集成电路制造工艺流程(0 学时) (5) 按比例缩小定律(1.5 学时) (6) 微电子技术的发展方向(1 学时) 2 本章教学要求:通过本章课程的学习,要求学生理解集成电路发展动态和趋势,掌握 集成电路中的材料及按比例缩小。 3 本章教学重点:理解摩尔定律以及按比例缩小定律。 4 本章教学难点:CE 率及 CV 率尺寸缩小前后的性能比较。 第二章:缩小到纳米尺寸的 CMOS 器件面临的挑战(12 学时)
研究生课程教学大纲 1本章教学内容: (1)尺寸缩小的限制(0.5学时) (2)尺寸缩小对工艺技术的挑战(0.5学时) (3)薄栅氧化层的问题(2学时) (4)多晶硅耗尽效应(1学时) (5)量子效应的影响(1学时) (6)迁移率退化与速度饱和(2学时) (7)杂质随机分布的影响(1学时) (8)阈值电压减小的限制(2学时) (9)源漏串联电阻的影响(2学时) 2本章教学要求:通过本章课程的学习,要求学生理解尺寸缩小的限制,掌握纳米尺度 CMOS所带来的一系列问题。 3本章教学重点:(1)多晶硅耗尽效应:(2)迁移率退化与速度饱对器件性能的影响: (3)源漏串联电阻与版图的关系及对性能影响分析。 4本章教学难点:(1)多晶硅耗尽推导,(2)源漏串联电阻与版图的关系分析。 第三章:超大规模集成物理(16学时) 1本章教学内容: (1)集成器件及模型(1学时) (2)集成电路中的电阻(1.5学时) (3)集成电路中的电容器(0.5学时) (4)集成电路中的电感(0.5学时) (5)二极管模型(0.5学时) (6)集成电路中的版图设计(3学时) (7)布局布线与寄生器件(1学时) (8)天线效应(0.5学时) (9)互联延迟(1.5学时) (10)串扰噪声(1学时) (11)小尺寸CM0S器件闩锁效应(1学时) (12)集成电路SD保护(2学时) (13)微电子封装技术(1学时) 2
研究生课程教学大纲 2 1 本章教学内容: (1) 尺寸缩小的限制(0.5 学时) (2) 尺寸缩小对工艺技术的挑战(0.5 学时) (3) 薄栅氧化层的问题(2 学时) (4) 多晶硅耗尽效应(1 学时) (5) 量子效应的影响(1 学时) (6) 迁移率退化与速度饱和(2 学时) (7) 杂质随机分布的影响(1 学时) (8) 阈值电压减小的限制(2 学时) (9) 源漏串联电阻的影响 (2 学时) 2 本章教学要求:通过本章课程的学习,要求学生理解尺寸缩小的限制,掌握纳米尺度 CMOS 所带来的一系列问题。 3 本章教学重点:(1)多晶硅耗尽效应;(2)迁移率退化与速度饱对器件性能的影响; (3)源漏串联电阻与版图的关系及对性能影响分析。 4 本章教学难点:(1)多晶硅耗尽推导,(2)源漏串联电阻与版图的关系分析。 第三章:超大规模集成物理(16 学时) 1 本章教学内容: (1)集成器件及模型(1 学时) (2)集成电路中的电阻(1.5 学时) (3)集成电路中的电容器(0.5 学时) (4)集成电路中的电感(0.5 学时) (5)二极管模型(0.5 学时) (6)集成电路中的版图设计(3 学时) (7)布局布线与寄生器件(1 学时) (8)天线效应(0.5 学时) (9)互联延迟(1.5 学时) (10)串扰噪声(1 学时) (11)小尺寸 CMOS 器件闩锁效应(1 学时) (12)集成电路 ESD 保护(2 学时) (13)微电子封装技术(1 学时)
研究生课程教学大纲 (14)集成电路及器件失效分析(1学时) 2本章教学要求:通过本章课程的学习,要求学生理解集成电路中的器件及模型,掌握 版图匹配,以及互联设计分析,SD保护设计考虑。 3本章教学重点:(1)集成电路中的版图设计与匹配,(2)集成器件与寄生器件模型。 4本章教学难点:(1)互联延迟设计考虑,(2)ESD保护结构原理。 第四章:纳米CMOS器件中的栅工程(6学时) 1本章教学内容: (1)CMOS器件中的MIS栅结构(1学时) (2)氯氧硅栅介质(1学时) (3)高介电常数栅介质(3学时) (4)纳米CMOS技术中的新型栅电极材料(1学时) 2本章教学要求:通过本章课程的学习,要求学生理解CMOS器件栅工程含义,掌握高 介电常数栅介质选择及器件设计考虑。 3本章教学重点:理解高介电常数栅介质MOSFET特性及FIBL效应。 4本章教学难点:(1)FIBL效应分析,(2)栅结构设计与栅电容计算。 第五章:纳米CMOS器件的沟道工程和超浅结技术(6学时) 1本章教学内容: (1)沟道工程要解决的问题(0.5学时) (2)纵向沟道工程(2学时) (3)纳米CMOS器件中的横向沟道工程(3学时) (4)纳米CM0S中的超浅结和相关离子掺杂新技术的发展(0.5学时) 2本章教学要求:通过本章课程的学习,要求学生掌握非均匀掺杂原理,理解衬底横向 与纵向沟道工程设计及优化。 3本章教学重点:纵向与横向沟道工程的性能比较分析。 4本章教学难点:泊松方程准二维求解。 第六章:新型纳米CMOS器件(6学时) 1本章教学内容: (1)新型衬底结构器件(2学时) 3
研究生课程教学大纲 3 (14)集成电路及器件失效分析(1 学时) 2 本章教学要求:通过本章课程的学习,要求学生理解集成电路中的器件及模型,掌握 版图匹配,以及互联设计分析,ESD 保护设计考虑。 3 本章教学重点:(1)集成电路中的版图设计与匹配,(2)集成器件与寄生器件模型。 4 本章教学难点:(1)互联延迟设计考虑,(2)ESD 保护结构原理。 第四章:纳米 CMOS 器件中的栅工程(6 学时) 1 本章教学内容: (1) CMOS 器件中的 MIS 栅结构 (1 学时) (2) 氮氧硅栅介质(1 学时) (3) 高介电常数栅介质(3 学时) (4) 纳米 CMOS 技术中的新型栅电极材料(1 学时) 2 本章教学要求:通过本章课程的学习,要求学生理解 CMOS 器件栅工程含义,掌握高 介电常数栅介质选择及器件设计考虑。 3 本章教学重点:理解高介电常数栅介质 MOSFET 特性及 FIBL 效应。 4 本章教学难点:(1)FIBL 效应分析,(2)栅结构设计与栅电容计算。 第五章:纳米 CMOS 器件的沟道工程和超浅结技术(6 学时) 1 本章教学内容: (1) 沟道工程要解决的问题(0.5 学时) (2) 纵向沟道工程(2 学时) (3) 纳米 CMOS 器件中的横向沟道工程(3 学时) (4) 纳米 CMOS 中的超浅结和相关离子掺杂新技术的发展(0.5 学时) 2 本章教学要求:通过本章课程的学习,要求学生掌握非均匀掺杂原理,理解衬底横向 与纵向沟道工程设计及优化。 3 本章教学重点:纵向与横向沟道工程的性能比较分析。 4 本章教学难点:泊松方程准二维求解。 第六章:新型纳米 CMOS 器件(6 学时) 1 本章教学内容: (1) 新型衬底结构器件(2 学时)
研究生课程教学大纲 (2)新型栅结构器件(2学时) (3)新型沟道结构器件(1学时) (4)无结M0S晶体管(1学时) 2本章教学要求:通过本章课程的学习,要求学生掌握S0 I MOSFET性能分析、FinFET 工作原理,理解应变的硅产生及对器件性能的影响。 3本章教学重点:SOI MOSFET的阈值电压与亚阈值斜率。 4本章教学难点:无结MOSFET的阈值电压模型。 三、教学方式 课程采取多媒体与板书相结合的方式授课,讲解与讨论相融合的教学方式。 四、考核方式与成绩评定 课程考核方式为考试,采取堂上开卷笔试的方式。 作业:作业根据课程进度情况分批布置,每章不少于一次。课堂作业同时可用于统计出 勤情况。 成绩评定的考核比例为: (1)过程考核占20%,包括: 考勤:5%,课堂互动:5%,平时作业:10%。 (2)期末考核占80%。 五、教材及主要参考书目 教材: [1]《纳米CMOS器件》,甘学温,黄如,刘晓彦,张兴著,科学出版社,2004年 参考书目: [l)《Advance Theory of Semiconductor Devices》,Karl Hess,IEEE Press,I999年。 [2]《集成电路设计》,叶以正,来逢昌,清华大学出版社,2016年。 [3)《模拟电路版图的艺术》,Alan Hastings,电子工业出版社,2013年。 [4《微电子器件》,陈星弼、陈勇、刘继芝、任敏,电子工业出版社,2018年。 4
研究生课程教学大纲 4 (2) 新型栅结构器件(2 学时) (3) 新型沟道结构器件(1 学时) (4) 无结 MOS 晶体管(1 学时) 2 本章教学要求:通过本章课程的学习,要求学生掌握 SOI MOSFET 性能分析、FinFET 工作原理,理解应变的硅产生及对器件性能的影响。 3 本章教学重点:SOI MOSFET 的阈值电压与亚阈值斜率。 4 本章教学难点:无结 MOSFET 的阈值电压模型。 三、教学方式 课程采取多媒体与板书相结合的方式授课,讲解与讨论相融合的教学方式。 四、考核方式与成绩评定 课程考核方式为考试,采取堂上开卷笔试的方式。 作业:作业根据课程进度情况分批布置,每章不少于一次。课堂作业同时可用于统计出 勤情况。 成绩评定的考核比例为: (1)过程考核占 20%,包括: 考勤:5%,课堂互动:5%,平时作业:10%。 (2)期末考核占 80%。 五、教材及主要参考书目 教材: [1]《纳米 CMOS 器件》,甘学温,黄如,刘晓彦,张兴著,科学出版社,2004 年 参考书目: [1]《Advance Theory of Semiconductor Devices》,Karl Hess ,IEEE Press, 1999 年。 [2]《集成电路设计》,叶以正,来逢昌,清华大学出版社,2016 年。 [3]《模拟电路版图的艺术》,Alan Hastings,电子工业出版社,2013 年。 [4]《微电子器件》,陈星弼、陈勇、刘继芝、任敏,电子工业出版社,2018 年
研究生课程教学大纲 03015001 Syllabus of Integrated Electronics Course Class 03015001 50 Code Course Hours Integrated Electronics Course ☑Degree Name Credit 2.5 Nature ▣Non-Degree☐Others Semester ( )Fall/(√)Spring Students (√)Master// )Ph.D Discipline Microelectronics and Solid State Electronics Physics of Semiconductors,Microelectronic Devices,Integrated Circuits, Prerequisites Semiconductor Technology School School of Electronic Science Engineering Reviewed Written by Chen Yong Date 2021.8 by 1.Course Objectives The course of Integrated Electronics focuses on the core and basic problems of integrated circuits.Through the teaching of this course,students can understand the development trends and technical trends of integrated circuits,master VLSI physics,the challenges and engineering technology solutions faced by nano CMOS integrated circuits,as well as new CMOS devices and integration technologies,and have the necessary core knowledge and solid foundation for the research and development of integrated circuits. 2.Course Content and Requirements Chapter1 Introduction to VLSI hours:4) (1)Development of integrated circuits (0.5h) (2)Magic Moore's law (0.5h) (3)Materials used in semiconductor technology (0.5h) (4)Integrated circuit manufacturing process (Oh) (5)Scaling down law (1.5h) (6)Development direction of microelectronic technology (Ih) The keys of this chapter are the Moore's law,materials used in semiconductor technology and the law of Scaling down.Through the study of this chapter,students are required to understand the development trends of integrated circuits,master the materials in integrated circuits and the scaling down law. 5
研究生课程教学大纲 5 03015001 Syllabus of Integrated Electronics Course Code 03015001 Course Name Integrated Electronics Class Hours 50 Course Nature Degree □Non-Degree□Others Credit 2.5 Semester ( )Fall/(√)Spring Students (√)Master/( )Ph.D Discipline Microelectronics and Solid State Electronics Prerequisites Physics of Semiconductors, Microelectronic Devices, Integrated Circuits, Semiconductor Technology School School of Electronic Science & Engineering Written by Chen Yong Reviewed by Date 2021.8 1. Course Objectives 《The course of Integrated Electronics focuses on the core and basic problems of integrated circuits. Through the teaching of this course, students can understand the development trends and technical trends of integrated circuits, master VLSI physics, the challenges and engineering technology solutions faced by nano CMOS integrated circuits, as well as new CMOS devices and integration technologies, and have the necessary core knowledge and solid foundation for the research and development of integrated circuits. 2. Course Content and Requirements Chapter1 Introduction to VLSI ( hours: 4 ) (1) Development of integrated circuits(0.5h) (2) Magic Moore's law(0.5h) (3) Materials used in semiconductor technology (0.5h) (4) Integrated circuit manufacturing process(0h) (5) Scaling down law(1.5h) (6) Development direction of microelectronic technology(1h) The keys of this chapter are the Moore's law, materials used in semiconductor technology and the law of Scaling down。Through the study of this chapter, students are required to understand the development trends of integrated circuits, master the materials in integrated circuits and the scaling down law
研究生课程教学大纲 Chapter2 Challenges faced by CMOS devices reduced to nano size(hours:12) (1)Limitation of size reduction (0.5h) (2)Challenge of size reduction to process technology (0.5h) (3)Problems of thin gate oxide (2h) (4)Polysilicon depletion effect (Ih) (5)Influence of quantum effect (Ih) (6)Mobility degradation and velocity saturation (2h) (7)Influence of impurity random distribution (Ih) (8)Limit of threshold voltage reduction (2h) (9)Influence of source drain series resistance (2h) This chapter describes a series of problems caused by nanoscale CMOS,such as TDDB, quantum effect,etc.Through the study of this chapter,students are required to understand the limitation of size reduction and master a series of problems caused by nanoscale CMOS. Chapter3 VLSI physics(hours:16) (1)Integrated devices and models (Ih) (2)Resistance in integrated circuits (1.5h) (3)Capacitors in integrated circuits (0.5h) (4)Inductance in integrated circuits (0.5h) (5)Diode model (0.5h) (6)Layout design in integrated circuits (3h) (7)Layout,wiring and parasitic devices (Ih) (8)Antenna effect (0.5h) (9)Interconnection delay (1.5h) (10)Crosstalk noise (Ih) (11)Latch up effect of small size CMOS devices (Ih) (12)Integrated circuit ESD protection (2h) (13)Microelectronic packaging (Ih) (14)Failure analysis of integrated circuits and devices (Ih) This chapter introduces the basic physical problems of integrated circuit design,including interconnection delay,parasitic effect,reliability and so on.Students are required to understand 6
研究生课程教学大纲 6 Chapter2 Challenges faced by CMOS devices reduced to nano size( hours: 12 ) (1) Limitation of size reduction(0.5h) (2) Challenge of size reduction to process technology(0.5h) (3) Problems of thin gate oxide(2h) (4) Polysilicon depletion effect(1h) (5) Influence of quantum effect(1h) (6) Mobility degradation and velocity saturation(2h) (7) Influence of impurity random distribution(1h) (8) Limit of threshold voltage reduction(2h) (9) Influence of source drain series resistance(2h) This chapter describes a series of problems caused by nanoscale CMOS, such as TDDB, quantum effect, etc. Through the study of this chapter, students are required to understand the limitation of size reduction and master a series of problems caused by nanoscale CMOS. Chapter3 VLSI physics( hours: 16 ) (1) Integrated devices and models(1h) (2) Resistance in integrated circuits(1.5h) (3) Capacitors in integrated circuits(0.5h) (4) Inductance in integrated circuits(0.5h) (5) Diode model(0.5h) (6) Layout design in integrated circuits(3h) (7) Layout, wiring and parasitic devices(1h) (8) Antenna effect(0.5h) (9) Interconnection delay(1.5h) (10) Crosstalk noise(1h) (11) Latch up effect of small size CMOS devices(1h) (12) Integrated circuit ESD protection(2h) (13) Microelectronic packaging(1h) (14) Failure analysis of integrated circuits and devices(1h) This chapter introduces the basic physical problems of integrated circuit design, including interconnection delay, parasitic effect, reliability and so on. Students are required to understand
研究生课程教学大纲 the devices and models in integrated circuits,to grasp the layout matching,and to design the interconnection,and to consider the design of ESD protection. Chapter4 Gate engineering in nano CMOS devices(hours:6) (1)MIS gate structure in CMOS devices (Ih) (2)Silicon oxynitride gate dielectric (Ih) (3)High dielectric constant gate dielectric (3h) (4)New gate electrode materials in nano CMOS technology (Ih) This chapter includes the gate engineering of CMOS device,describes the characteristics of high dielectric constant gate dielectric MOSFET and FIBL effects.Through the study of this chapter,students are required to master the FIBL effects,design considerations of high dielectric constant gate dielectric devices and gate capacitance calculation of nanoscale MOSFET's Chapter5 Channel engineering and ultra shallow junction technology of nano CMOS devices(hours:6) (1)Problems to be solved in channel engineering (0.5h) (2)Vertical channel engineering (2h) (3)Horizontal channel engineering in nano CMOS devices (3h) (4)Development of ultra shallow junction and related ion doping in nano CMOS (0.5h) Through the study of this chapter,students are required to understand principle of non-uniform doping,and master the design and optimization of the transverse and longitudinal channel engineering Chapter6 Novel nano CMOS devices hours:6) (1)Novel substrate structure device (2h) (2)New gate structure device (2h) (3)New channel structure device (Ih) (4)Junctionless MOS transistor (Ih) This chapter explains the performance analysis of SOI MOSFET,working principle of FinFET,and strain silicon technology.Through the study of this chapter,students are required to master threshold voltage and subthreshold slope of SOI MOSFET,working principle of FinFET
研究生课程教学大纲 7 the devices and models in integrated circuits, to grasp the layout matching, and to design the interconnection, and to consider the design of ESD protection. Chapter4 Gate engineering in nano CMOS devices( hours: 6 ) (1) MIS gate structure in CMOS devices(1h) (2) Silicon oxynitride gate dielectric(1h) (3) High dielectric constant gate dielectric(3h) (4) New gate electrode materials in nano CMOS technology(1h) This chapter includes the gate engineering of CMOS device , describes the characteristics of high dielectric constant gate dielectric MOSFET and FIBL effects. Through the study of this chapter, students are required to master the FIBL effects, design considerations of high dielectric constant gate dielectric devices and gate capacitance calculation of nanoscale MOSFET’s. Chapter5 Channel engineering and ultra shallow junction technology of nano CMOS devices( hours: 6 ) (1) Problems to be solved in channel engineering(0.5h) (2) Vertical channel engineering(2h) (3) Horizontal channel engineering in nano CMOS devices(3h) (4) Development of ultra shallow junction and related ion doping in nano CMOS(0.5h) Through the study of this chapter, students are required to understand principle of non-uniform doping, and master the design and optimization of the transverse and longitudinal channel engineering. Chapter6 Novel nano CMOS devices ( hours: 6 ) (1) Novel substrate structure device(2h) (2) New gate structure device(2h) (3) New channel structure device(1h) (4) Junctionless MOS transistor(1h) This chapter explains the performance analysis of SOI MOSFET, working principle of FinFET, and strain silicon technology. Through the study of this chapter, students are required to master threshold voltage and subthreshold slope of SOI MOSFET ,working principle of FinFET
研究生课程教学大纲 and junctionless nanoscale CMOS 3.Teaching Methods The course adopts a combination of multimedia and blackboard writing,and a combination of explanation and discussion. 4.Evaluation and Grading The course assessment method is examination,which adopts the open book written examination in class. Homework:Homework shall be arranged in batches according to the course progress,and each chapter shall not be less than once.Class assignments can also be used to count attendance. The assessment proportion of performance evaluation is: (1)Process assessment accounts for 20%,including: Attendance:5%.classroom interaction:5%.usual homework:10% (2)The final examination accounts for 80%. 5.Teaching Materials &References (Including Author,Title,Publisher and Publishing Time) Textbook: 《纳米CMOS器件》,甘学温,黄如,刘晓彦,张兴著,科学出版社,2004年。 Reference: [1]Advance Theory of Semiconductor Devices),Karl Hess IEEE Press,1999. [2]《集成电路设计》,叶以正,来逢昌,清华大学出版社,2016年。 [3)《模拟电路版图的艺术》,Alan Hastings,电子工业出版社,2013年。 [4《微电子器件》,陈星弼、陈勇、刘继芝、任敏,电子工业出版社,2018年。 8
研究生课程教学大纲 8 and junctionless nanoscale CMOS. 3. Teaching Methods The course adopts a combination of multimedia and blackboard writing, and a combination of explanation and discussion. 4. Evaluation and Grading The course assessment method is examination, which adopts the open book written examination in class. Homework: Homework shall be arranged in batches according to the course progress, and each chapter shall not be less than once. Class assignments can also be used to count attendance. The assessment proportion of performance evaluation is: (1) Process assessment accounts for 20%, including: Attendance: 5%, classroom interaction: 5%, usual homework: 10%. (2) The final examination accounts for 80%. 5. Teaching Materials &References (Including Author, Title, Publisher and Publishing Time) Textbook: 《纳米 CMOS 器件》,甘学温,黄如,刘晓彦,张兴著,科学出版社,2004 年。 Reference: [1]《Advance Theory of Semiconductor Devices》,Karl Hess ,IEEE Press, 1999. [2]《集成电路设计》,叶以正,来逢昌,清华大学出版社,2016 年。 [3]《模拟电路版图的艺术》,Alan Hastings,电子工业出版社,2013 年。 [4]《微电子器件》,陈星弼、陈勇、刘继芝、任敏,电子工业出版社,2018 年