ENTITY cmpl sig IS ENTITY PORT(a, b, sel: IN bit; X, y, Z: OUT bit ARCHITECTURE END cmpl_sig ARCHITECTURE logic OF cmpl_sig IS BEGIN simple signal assignment abeab k X c(a AND NoT sel) OR(b AND sel); conditional signal assignmer y caHeN sel=O ELSE selected signal assignment WITH sel SElECT sel z < a WHEN 'O b WHEN Z 0 WHEN OTHERS: END logic; CONFIGURATION cmpl_sig_ conf OF cmpl_sig IS FOR logic END FOR END cmpl sig conf设计中心 Putting it all together