esTc 设计中 (1)Simple Signal Assignment This kind of statements are executed in parallel Enti tity testl is (02 port ( a, b, e: in bit; C, d: out bit); OUtPitpa end testI; architecture testl body of testl is begin c<=a and b d<=e; end testl body设计中心 (1) Simple Signal Assignment • This kind of statements are executed in Parallel Entity test1 is port ( a, b, e : in bit; c, d : out bit); end test1; architecture test1_body of test1 is begin c <= a and b; d <= e; end test1_body;