Up/down counters are FSms Asyn. clock -more delay among outputs, less logic the output of one state register is the clock of another state register Syn clock -less delay among outputs more logic all clock inputs of state registers (flip-lops are connected Examples here are all Moore machines (output depends on state registers. VHDL 6. examples of FSM ver. 8aUp/down counters are FSMs • Asyn.clock -more delay among outputs, less logic – the output of one state register is the clock of another state register. • Syn. clock -less delay among outputs, more logic – all clock inputs of state registers (flip-lops) are connected. • Examples here are all Moore machines (output depends on state registers.) VHDL 6. examples of FSM ver.8a 3