vords deen The first s of the wizard is shown in figure 5 Since this m includes a register for synchronously loading addresses.This register is required due to the design of the memory resources on the Cyclone II FPGA;account for the clocking of this address register in your design To place processor instructions into the memory,you need to specify initial values that should be stored in the memory once your circuit has been programmed into the FPGA chip.This can be done by telling the ze the memory using the cont a me screen which then has to he created in the direc ins the Qua ect Ilse the Quartus on-n Helpto lea about the format of theand createthat hasr instructions to test your circuit. 3epesiaoeaeticlBarctasedpopeodofeoMandamd pin loca e e for MClock,and useKEY for PClock Connect the processor bus wires toRand connect the Done signal to LEDR17. 5.Compile the circuit and download it into the FPGA chip. MegaWizard Plug-n Manager-ALTSYNCRAM [page 1 of Curertly selected device famiy:Cclonell H Wih one read port [ROM model With two read/write ports [Tue dual-port mode) inst_mem dess时4.01 As a numbet of words Block Type:A Figure 5.ALTSYNCRAM configuration. 7 words deep. The first screen of the wizard is shown in Figure 5. Since this memory has only a read port, and no write port, it is called a synchronous read-only memory (synchronous ROM). Note that the memory includes a register for synchronously loading addresses. This register is required due to the design of the memory resources on the Cyclone II FPGA; account for the clocking of this address register in your design. To place processor instructions into the memory, you need to specify initial values that should be stored in the memory once your circuit has been programmed into the FPGA chip. This can be done by telling the wizard to initialize the memory using the contents of a memory initialization file (MIF). The appropriate screen of the MegaWizard Plug-In Manager tool is illustrated in Figure 6. We have specified a file named inst_mem.mif, which then has to be created in the directory that contains the Quartus II project. Use the Quartus II on-line Help to learn about the format of the MIF file and create a file that has enough processor instructions to test your circuit. 3. Use functional simulation to test the circuit. Ensure that data is read properly out of the ROM and executed by the processor. 4. Make sure your project includes the necessary port names and pin location assignments to implement the circuit on the DE2 board. Use switch SW17 to drive the processor’s Run input, use KEY0 for Resetn, use KEY1 for MClock, and use KEY2 for PClock. Connect the processor bus wires to LEDR15−0 and connect the Done signal to LEDR17. 5. Compile the circuit and download it into the FPGA chip. 6. Test the functionality of your design by toggling the switches and observing the LEDs. Since the circuit’s clock inputs are controlled by push button switches, it is easy to step through the execution of instructions and observe the behavior of the circuit. Figure 5. ALTSYNCRAM configuration. 7