0p3 0 Sta End 400m 200n 600n 2400n Name X10 02a00X00500m5⑩0m5 Figure 3.Simulation of the processo Part II In this part you are to de n Fig whichamemory moduleand 1 this data is provided to the processor as a stream of instruction.Tosimplify the design and testing of this circuit we have used separate clock signals,PClock and MClock,for the processor and memory. MClock PClock Resetn Run Figure 4.Connecting the processor to a memory and counter 1.Create a new Quartus II project which will be used to test your circuit 2 Generate a ton-level vHDL file that instantiates the d counter Use the ouartus I Megawizard Plug-n Manager tool to create the memory module from the Altera library of parameterized modules(LPMs).The comrect LPM is found under the storage eategory and is called ALTSYNCRAM Follow the instructions provided by the wizard to create a memory that has one 16-bit wide read data port and is 32Figure 3. Simulation of the processor. Part II In this part you are to design the circuit depicted in Figure 4, in which a memory module and counter are connected to the processor from Part I. The counter is used to read the contents of successive addresses in the memory, and this data is provided to the processor as a stream of instructions. To simplify the design and testing of this circuit we have used separate clock signals, PClock and MClock, for the processor and memory. Counter n Resetn MClock Memory 16 addr data Processor 16 DIN Bus Resetn Run Done Run Bus Done PClock Figure 4. Connecting the processor to a memory and counter. 1. Create a new Quartus II project which will be used to test your circuit. 2. Generate a top-level VHDL file that instantiates the processor, memory, and counter. Use the Quartus II MegaWizard Plug-In Manager tool to create the memory module from the Altera library of parameterized modules (LPMs). The correct LPM is found under the storage category and is called ALTSYNCRAM. Follow the instructions provided by the wizard to create a memory that has one 16-bit wide read data port and is 32 6