上升沿D触发器描述 方法二:使用WAIT语句 BRARY EEE USE IEEESTD LOGIC 1164ALL: ENTITY D reg Is PORTOD,CP: IN STD LOGIC; Q: OUT STD LOGIC); END D reg: ARCHITECTURE test OFD reg Is BEGIN PROCESS BEGIN WAIT UNTIL CP=1 Q<=D END PROCESS END test方法二：使用WAIT 语句 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY D_reg IS PORT(D,CP:IN STD_LOGIC; Q:OUT STD_LOGIC); END D_reg; ARCHITECTURE test OF D_reg IS BEGIN PROCESS BEGIN WAIT UNTIL CP=‘1’; Q<=D; END PROCESS; END test; 上升沿D触发器描述