Active HDL 6.1 (wdt wdt)-D: My Designs\wdt\wdt\src\mux. vhd File Edit Search View Workspace Design Simulation Tools window Help 值回淼圃梦品Bm曾9B求虑 Design Browser example library ieee: 非 example:mu(mix) entity mux is ogic 1164.all: use leee. std l 非m:mw(beh1) Sline 11 port(in1, in2, sel:in sta logic; c: out std logic): 中非u2:and2(rt) end mux: 非u3:and2(rtl architecture mix。正muXi C line 22 component Inv std standard port(a: in std logiC. ieee std logic 1 164 10 b: out sta工oqic) end component: component and2 prt(a,b: in sto工ogic 14 c: out sta logic): 15 end component: Name value 16 signal notsel:std logic; sIdna1m1;m2:std工oqc b Unay begin u1: inv port map (a=>sel,b=>notsel): u2: and2 port map(sel, in1, m1): u3: and2 port map(notsel, in2, m2) C<=m1 or m2: a ml 24 configuration example of mux is 5 for m]x for u1: inv use entity inv (beh1): end for. 29 end ex