Active HDL 6.1 (wdtwdt)-D: My Designs\wdt\wdt\src\mux. vhd File Edit Search View Workspace Design Simulation Tools Window Help 副器圃梦扁m?6|B均 Design Browser oi. port Example library ieee: use ieee. std logic 1164.all: Unsorted entity mux 1s Gii workspace'wdt': 1 port(in1, in2, sel:in std logic; wdt c: ut std工oqc) E Add New File end mux Eswtv architecture mix of nux 1s 自√ / ipad.vh component lnv i rtl awF port(a: in std工oqic bko2, awF b: out st工oqic) 自√ half. vhd end component: 4中Jha2vhd component and2 中圉Jinv,vhd port〔a,b: in std工oqic td工oqc) (beh) end component: Fast signal notsel: std logic. signal m1,m2: sta logic; begin 自√Jand2vhd u1: inv port map (a=>sel,b=>notsel): EAI and2 (rtl) 20 u2: and2 port map(sel, in1, m1); 自√ mux. vhd 21 u3: and2 port map (notsel, in2, m2): EAl mux(mix) c<=m1 or m2; end rmix. wdt library configuration example of mux is 。xmix for ul: inv use entity inv (beh1): 27 end for: 28 end for: end exarmp le