Section 1.10 Digital-Design Levels 21 74x157 A 2Y 11 3A 10 3Y Figure 1-10 Logic diagram for a 13 4B 4Y We can also realize the multiplexer function as part of a programmable logic device.Languages like ABEL allow us to specify outputs using Boolean equations similar to the one on the previous page,but it's usually more conve- nient to use "higher-level"language elements.For example,Table 1-2 is an name of th will be realized.The next two lines specify the device pin numbers for inputs and output.The"WHEN"statement specifies the actual logic function in a way that's very easy to understand,even though we haven't covered ABEL yet An even higher level language,VHDL,can be used to specify the multi- plexer function in a way that is very flexible and hierarchical.Table 1-3 is an example VHDL program for the multiplexer.The first two lines specify a standard library and set of definitions to use in the design.The next four lines specify only the inputs and outputs of the function,and purposely hide any details about the way the function is realized internally.The "architecture" section of the program specifies the function's behavior.VHDL syntax takesa little getting used to,but the single "when"statement says basically the same thing that the ABEL version did.A VHDL "synthesis tool"can start with this module chapimux Table 1-2 ABEL program for the multiplexer 28,8 g盟6a3e‘eoe equations WHEN S ==0 THEN Z A;ELSE Z B: end chapimux Copyright 1999 by John F.Wakerly Copying ProhibitedSection 1.10 Digital-Design Levels 21 DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY Copyright © 1999 by John F. Wakerly Copying Prohibited We can also realize the multiplexer function as part of a programmable logic device. Languages like ABEL allow us to specify outputs using Boolean equations similar to the one on the previous page, but it’s usually more conve￾nient to use “higher-level” language elements. For example, Table 1-2 is an ABEL program for the multiplexer function. The first three lines define the name of the program module and specify the type of PLD in which the function will be realized. The next two lines specify the device pin numbers for inputs and output. The “WHEN” statement specifies the actual logic function in a way that’s very easy to understand, even though we haven’t covered ABEL yet. An even higher level language, VHDL, can be used to specify the multi￾plexer function in a way that is very flexible and hierarchical. Table 1-3 is an example VHDL program for the multiplexer. The first two lines specify a standard library and set of definitions to use in the design. The next four lines specify only the inputs and outputs of the function, and purposely hide any details about the way the function is realized internally. The “architecture” section of the program specifies the function’s behavior. VHDL syntax takes a little getting used to, but the single “when” statement says basically the same thing that the ABEL version did. A VHDL “synthesis tool” can start with this module chap1mux title 'Two-input multiplexer example' CHAP1MUX device 'P16V8' A, B, S pin 1, 2, 3; Z pin 13 istype 'com'; equations WHEN S == 0 THEN Z = A; ELSE Z = B; end chap1mux Table 1-2 ABEL program for the multiplexer. 74x157 1A 1B 2A 2B 3A 3B 4A 4B G 2 4 1Y 7 2Y 9 3Y 12 4Y 3 5 6 11 10 14 13 S 1 15 S B A Z Figure 1-10 Logic diagram for a multiplexer using an MSI building block