Buffering the clock Buffering the clock ◆ Buffering ◆ Clock tree All in same IC package Even this may produce excessive clock skew if one clock is loaded much more heavily than the othe Transitions on the more heavily loaded clock appear to CLK1 CLK1 ries to balance the loads on multiple clocks CLK2 CLK2 CLS CLK1 Controllable Clock Skew CLK3 Gating the clock DFF with Gated Clock O How not to gate the clock CLK. GCL Simple-minded circuit CLKEN CLK o74X3778-bit register with gated clock elf EN is asserted at the rising edge of the clock Timing diagram then the DFFs are loaded from the data inputs GCLK e Otherwise, they retain their present values Synchronizer Synchronizer Failure° ◆同步器用于同步异步输入 ◆若在同步器输出仍处于亚稳态时使用该信号,将 产生难以预料的结果,称 Synchronizer Failure SYNCIN ASYNCIN ASYNCIN asynchronous input) CLOCK CLOCK6 46 Buffering the clock ‹Buffering Excessive Clock skew Controllable Clock Skew CLK CLK CLK1 CLK2 CLK CLK1 CLK2 CLK3 All in same IC package 47 Buffering the clock ‹Clock Tree z Even this may produce excessive clock skew if one clock is loaded much more heavily than the other z Transitions on the more heavily loaded clock appear to occur later z Tries to balance the loads on multiple clocks CLK CLK1 CLK2 CLK3 All in same IC package 48 Gating the clock ‹How not to gate the clock Simple-minded circuit CLK GCLK CLKEN CLK GCLK CLKEN Timing diagram 50 DFF with Gated Clock ‹74X377 8-bit register with gated clock zIf EN is asserted at the rising edge of the clock, then the DFFs are loaded from the data inputs zOtherwise，they retain their present values D Q 8D CLK EN Q 8Q 51 Synchronizer ‹同步器用于同步异步输入 52 Synchronizer FailureC ‹若在同步器输出仍处于亚稳态时使用该信号，将 产生难以预料的结果，称Synchronizer Failure