e.g. 3 Traffic Light Controller+ 5.3 Sequential Logic DesignA18 Digital Design: 8.1: 8.8: 8.9 Timing Diagrams Specifications Synchronizer Failure and Metastability o Traffic sensors and signals in an intersection. sunnyvale, California 5.3 Timing Diagrams Specifications 5.3 Timing diagrams ◆ Timing Diagram ◆ Set-up time margin XXXXXXXX XXX XXXXXXXX ∝ XXXXXXXXXXX Flip-Flop XXXXXXXXXXXXXX Set-up time margin t-td(max -tomb(max tsu, must be greate Timing Diagrams Impediments to Sync. Design ◆ Hold time margin ◆ Clock skew CLOCK tpd(Min)+comb(Min -th-tskew(max) >0 Q1 XXXXXXXX XXXXXXXXXXXXX Hold time margin tpd(Min +comb(Min th, must be greater than A long slow path: skew 55 30 e.g.3 Traffic Light Controller自学 ‹Traffic sensors and signals in an intersection, Sunnyvale, California 40 5.3 Sequential Logic DesignA18 ‹Digital Design: 8.1; 8.8; 8.9 z Timing Diagrams & Specifications z Impediments to Synchronous Design z Synchronizer Failure and Metastability 41 5.3 Timing Diagrams & Specifications ‹Timing Diagram tclk tsu th tcomb tpd tpd CLOCK Flip-Flop outputs Combinational outputs Flip-Flop Inputs 42 5.3 Timing Diagrams & Specifications ‹Set-up time margin z Set-up time margin tclk-tpd(max)-tcomb(max)-tsu , must be greater than 0 tclk Setup-time margin tsu th tcomb tpd tpd CLOCK Flip-Flop outputs Combinational outputs Flip-Flop Inputs 43 Timing Diagrams ‹Hold time margin z Hold time margin tpd(Min)+tcomb(Min)-th , must be greater than 0 Hold-time margin CLOCK tpd Flip-Flop outputs Combinational outputs Flip-Flop Inputs tclk tsu th tcomb tpd 45 Impediments to Sync. Design* ‹Clock Skew In CP D Q D Q A B Q1 Q2 A long slow path: tskew tpd(Min)+tcomb(Min)-th -tskew(max) >0 tpd(Min)+tcomb(Min)-th>0 Comb