52同步时序电路设计尖践 e.g. 1 T-bird Tail Lights o Digital Design: 7.5: 7.6: 7.7: 7.8 ◆雷鸟车尾灯 ◆同步时序电路设计流程 每边各有3个灯:轮流顺序亮起,表示车的转向 ●原始状态转移图,状态化简和编码 ●三个输入:左转:右转:应急闪烁输入 ●建立状态转移输出表 ◆功能 ●导出状态方程、激励方程和输出方程 ●转向状态:6个灯轮流协调闪炼 ●画时序电路逻辑图 ●告警状态 ●检查电路:避免挂起(该步骤有时可省略 ◆同步时序电路设计方法 ●逻辑电路 圆■圆 ●VHDL描述 ZOTTFFS e.g.1 T-bird Tail Lights ou ::::: e.g.1 T-bird Tail Lights ;;;。8 Output Tabl State LC LB LA RA RB RC IDLE000000 L1001000 0000 左工了右 000110 0001 转 转 LR31111 凸凸凸凸凸凸 左Lc-1 3 LA RA RB RC右 转回回[[转 e.g.1 T-bird Tail Lights e.g.1 T-bird Tail Lights ◆8状态 ◆状态图完善1 ●原始图有问题 ●左转,右转 无法处理多输入(L3 ●HAZ告警,且 有效的情形 同时左转和右 转不清醒 (L+R+H)( Idle Tab (L+R+H) H+L,R E0。000 L RH
1 4 5.2 同步时序电路设计实践 Digital Design: 7.5; 7.6; 7.7; 7.8 同步时序电路设计流程 z 原始状态转移图，状态化简和编码 z 建立状态转移/输出表 z 导出状态方程、激励方程和输出方程 z 画时序电路逻辑图 z 检查电路：避免挂起 (该步骤有时可省略) 同步时序电路设计方法 z 逻辑电路 z VHDL描述 5 e.g.1 T-bird Tail Lights 雷鸟车尾灯 z 每边各有3个灯：轮流顺序亮起，表示车的转向 z 三个输入：左转；右转；应急闪烁输入 功能 z 转向状态：6个灯轮流协调闪烁 z 告警状态 6 e.g.1 T-bird Tail Lights LC LB LA 左 转 RA RB RC 右 转 7 e.g.1 T-bird Tail Lights 左 LC LB LA 转 RA RB RC 右 转 8 e.g.1 T-bird Tail Lights 8状态 z原始图有问题 无法处理多输入 有效的情形 LR3 Left Idle R1 R2 R3 L1 L2 L3 Right 1 1 1 1 1 1 (L+R+H)’ 1 HAZ 9 e.g.1 T-bird Tail Lights 状态图完善1 z左转，右转 zHAZ告警，且 同时左转和右 转……不清醒 LR3 L⋅R’⋅H’ Idle R1 R2 R3 L1 L2 L3 1 1 1 1 1 1 1 H+L⋅R L’⋅R⋅H’ (L+R+H)’
e.g. 1 T-bird Tail Lights e.91 T-bird Tail Lights(筒化的状态 ◆状态图完善2 ◆状态方程 意完备性! ●一有可能就进 Q=2212。(HA2+Rig 入告警模式 +Q2Q·HLAz+Q2Q 较安全 LR. ●状态图修改2 c"=g2Q1HAz·(Lef⊕Rghr L+R+H Idl H+LR +0,Q- HAZ L∵R,H ◆转换为激励方程 ◆逻辑电路 VHDL for theT-bird Tail Lights VHDL(Cont, oess(CLOCK) Use IEEE std_logic_1164.all Entity Abird is SET =1"then Lights if HAZ='1 then Lights LIGHTS 最小风险:使成为全喷定的状态图 ●时钟频率4Hz 最小成本:使成为光全确定的状态图 ●猜谜:按下1个按钮,某输 时钟触发沿到来前有效的灯 效,未能猜中:若相同为猜中。一旦 停止并且ERR输出会维持1个或多个时钟周期,直到输 入G取消,游戏继续进行
2 10 e.g.1 T-bird Tail Lights 状态图完善2 z一有可能就进 入告警模式比 较安全 z状态图修改2 LR3 L⋅R’⋅H’ Idle R1 R2 R3 L1 L2 L3 1 1 1 1 1 1 1 H+L⋅R L’⋅R⋅H’ (L+R+H)’ H H H H H’ H’ H’ H’ 12 e.g.1 T-bird Tail Lights 状态方程 转换为激励方程 逻辑电路… 1 2 210 2 0 20 ( ) n Q Q Q Q HAZ Right Q Q HAZ Q Q + = ⋅⋅⋅ + +⋅⋅ +⋅ Q Q HAZ n = ⋅ + 0 1 1 1 0 21 1 0 ( ) n Q Q Q HAZ Left Right Q Q HAZ + = ⋅⋅ ⋅ ⊕ +⋅⋅ 简化的状态 转移表 注意完备性! 13 VHDL for theT-bird Tail Lights Library IEEE; Use IEEE.std_logic_1164.all; Entity Vtbird is port ( Clock, Reset, Left, Right, HAZ: in Std_Logic; LIGHTS: buffer Std_Logic _Vector (1 to 6) ); --LC LB LA RA RB RC End; Architecture Vtbird_arch of Vtbird is Constant Idle : Std_Logic _Vector (1 to 6) := "000000"; Constant L1 : Std_Logic _Vector (1 to 6) := “001000"; Constant L2 : Std_Logic _Vector (1 to 6) := “011000"; Constant L3 : Std_Logic _Vector (1 to 6) := "111000"; Constant R1 : Std_Logic _Vector (1 to 6) := "000100"; Constant R2 : Std_Logic _Vector (1 to 6) := "000110"; Constant R3 : Std_Logic _Vector (1 to 6) := "000111"; Constant LR3 : Std_Logic _Vector (1 to 6) := "111111"; 14 VHDL(Cont.) VHDL(Cont.) Begin Process (CLOCK) Begin If CLOCK'event and CLOCK = '1' then If RESET = '1' then Lights If HAZ='1' or (Left='1' and Right='1') then Lights if HAZ='1' then Lights if HAZ='1' then Lights LIGHTS if HAZ='1' then Lights if HAZ='1' then Lights LIGHTS LIGHTS null; End case; End if; End if; End process; End Vtbird_arch; LR3 L⋅R’⋅H’ Idle R1 R2 R3 L1 L2 L3 1 1 1 H+L⋅R L’⋅R⋅H’ (L+R+H)’ H H H H H’ H’ H’ H’ LR3 L⋅R’⋅H’ Idle R1 R2 R3 L1 L2 L3 1 1 1 H+L⋅R L’⋅R⋅H’ (L+R+H)’ H H H H H’ H’ H’ H’ 15 小结 完全描述的同步时序电路 z确定状态图 非完全描述的同步时序电路 z确定状态图 z按设计需求，更改状态图，确定合理的状态转移 ¾最小风险：使成为完全确定的状态图 ¾最小成本： 使成为完全确定的状态图 16 e.g.2 猜谜游戏 同步状态机 z 4个按钮，与输入G1~G4联接 z 1个ERR输出，与红色指示灯联接 z 4个输出，与指示灯L1~L4联接，并与对应输入相邻 功能 z 正常情况下，每经过1个时钟，模式旋转1个位置 z 时钟频率4Hz z 猜谜：按下1个按钮，某输入Gi 有效；若当前输入数Gi 与 时钟触发沿到来前有效的灯输出(状态)不同，则ERR有 效，未能猜中；若相同为猜中。一旦完成1次猜测，游戏 停止并且ERR输出会维持1个或多个时钟周期，直到输 入Gi 取消，游戏继续进行 G1 G2 G3 G4 L1 L2 L3 L4 ERR
e.g. 2 Guessing Game e.g.2 Guessing Game ◆5状态 ◆6状态 无法指示猜测结 果是否正确 G1263G G1G2G3.G ◆使用者同时按下 多个按键 需克服并进入 G2 G3.Ga 6263 ERR状态 G+G GaG G1G2G3 Guessing Game Guessing Game ◆ Gray-Coded State Assignment圖 o Gray-Coded State Assignment Moore状态机,输出方程为 s301 ERRE 状态方程可转换为激励方程:略 sm::1 对此1: Output- Coded State Assign 对比1: Output- Coded State Assign QOutput-Coded State Assignment oOutput-Coded State Assignment ●也可以用输出作为状态变量 直接用输出作为状态变量,得到输出方程为 =L…,L, L2., ERR(G43G2)●方程组并不简 00 or,aayor .i3·L2LERR·(G4G3 单,但输出数 x"=l4l2l2,z1,ERR、GG3G2G)变少(50) ERR+=L4. L,L,L, 0090 G4+G2+G1) 9 +L4.,Lz.. ERR +1·L12L·ER(G3+G2+G) +·z21·ERRG4+G+G2+G)
3 17 e.g.2 Guessing Game 5状态 无法指示猜测结 果是否正确 使用者同时按下 多个按键 需克服并进入 ERR状态 Stop S1 S2 S3 S4 G1 ’ .G2’. G3’.G4’ G1+G2+G3+G4 G1+G2+G3+G4 G1+G2+G3+G4 G1+G2+G3+G G 4 1 ’ .G2’.G3’.G4’ G1 ’ .G2’.G3’.G4’ G1 ’ .G2’.G3’.G4’ G1 ’ .G2’.G3’.G4’ G1+G2+ G3+G4 18 e.g.2 Guessing Game 6状态 SErr S1 S2 S3 S4 G1 ’ .G2’.G3’.G4’ G1+G3+G4 G1+G2+G4 G1+G2+G3 G2+G3+G4 G1 ’ .G2’.G3’.G4’ G1 ’ .G2’.G3’.G4’ G1 ’ .G2’.G3’.G4’ G1 ’ .G2’.G3’.G4’ SOK G1 ’ .G2.G3’.G4’ G1 ’ .G2’.G3.G4’ G1 ’ .G2’.G3’.G4 G1.G2’.G3’.G4’ G1+G2+ G3+G4 G1+G2+ G3+G4 G1 ’ .G2’.G3’.G4’ 20 Guessing Game Gray-Coded State Assignment 状态 Q2 Q1 Q0 S1 0 0 0 S2 0 0 1 S3 0 1 1 S4 0 1 0 SOK 1 0 0 SErr 1 0 1 21 Guessing Game Gray-Coded State Assignment zMoore状态机，输出方程为 z状态方程可转换为激励方程：略…… 2 1 0 1 L4 Q Q Q n = ⋅ ⋅ + 2 1 0 1 L3 Q Q Q n = ⋅ ⋅ + 2 1 0 1 L2 Q Q Q n = ⋅ ⋅ + 2 1 0 1 L1 Q Q Q n = ⋅ ⋅ + ERR Q2 Q1 Q0 = ⋅ ⋅ 状态 Q2 Q1 Q0 S1 0 0 0 S2 0 0 1 S3 0 1 1 S4 0 1 0 SOK 1 0 0 SErr 1 0 1 22 Output-Coded State Assignment z也可以用输出作为状态变量 对比1：Output-Coded State Assign. Output-Coded State Assign. 23 Output-Coded State Assignment z直接用输出作为状态变量，得到输出方程为 对比1：Output-Coded State Assign. Output-Coded State Assign. ( 4 3 2 1) 1 4 3 2 1 L2 L L L L ERR G G G G n = ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ + 1 ( 4 3 2 1) 2 4 3 1 L3 L L L L ERR G G G G n = ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ + 2 1 ( 4 3 2 1) 3 4 1 L4 L L L L ERR G G G G n = ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ + 3 2 1 4 3 2 1 ( 4 3 2 1) 1 L1 L L L ERR L L L L G G G G n = ⋅ ⋅ ⋅ + ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ + （ ） 1 4321 432 43 1 2 431 4 21 3 421 321 4 321 4321 4321 ( ) ( ) ( ) ( ) ( ) n ERR L L L L ERR G G G L L L L ERR G G G L L L L ERR G G G L L L L ERR G G G L L L L ERR G G G G + = ⋅⋅⋅⋅ ⋅ + + +⋅⋅⋅⋅ ⋅ + + +⋅⋅⋅⋅ ⋅ + + +⋅ ⋅ ⋅⋅ ⋅ + + +⋅⋅⋅⋅ ⋅ + + + z方程组并不简 单，但输出数 变少(5Æ0)
对比2: Unused states Treatment 对此2: Unused States Treatment uNused States Treatment oOutput-Coded State Assignment ●状态图有6个状态 ●限制:机器不小心进入“未用状态”,可以自动回 ●实际5个触发器有32个状态,未用状态作为“无关 到正常”状态 ●自由度:通过引入“无关项”,允许对逻辑电路作 Karnaugh Map化筒只能处理莓单问题“……艹 计算机化简:许多综合软件易处理大舰模 一定的简化— Minimal cost apporach 计但却无活处理无近 般需要设计者单独写一段处理代码:; :: 对比2; Unused States Treatment VHDL for the Guessing game Machine OOutput-Coded State Assignment Use IEEE std_logic_1164.all, Port( Clock, Reset, G1, G2, G3. G4 L1,L2,L3,L4,E Out STD Logic): Type Sreg_type is(ST, S2, S3, S4, SOK, SERR) ●输出简化,例如ERR=4(G+G+G2) 可以证明,最简或与+l2L1G4+G3+G) 1 when S L2 If G2=1 or G3*" or G4*1 then Sreg s SERR The original quessing game is easy to win after s2s If GrrorG3 minute of practice because the lamps cycle at a very consistent rate of 4Hz when S3=> If G1=1or G4=t' then triple the clock speed but allow the lamps to stay when sas>f Gier or G2etr' or G3=r then sg in each state for a random length of time The user truly must guess whether a given lamp when SOK I SERR = If G1=0 an will stay on long enough for the corresponding pushbutton to be pressed when others => Sreg <s S1 Add an enable input, which is driven by the End case: S,Huca a Linear Feedback Shift Register(LFSR) End vggame_ arch
4 24 Unused States Treatment z状态图有6个状态 z实际5个触发器有32个状态，未用状态作为“无关 状态” zKarnaugh Map化简：只能处理简单问题 z计算机化简：许多综合软件容易处理大规模设 计，但却无法处理 “无关项”； 一般需要设计者单独写一段处理代码 对比2：Unused States Treatment Unused States Treatment 25 Output-Coded State Assignment z限制：机器不小心进入“未用状态”，可以自动回 到“正常”状态 z自由度：通过引入“无关项”，允许对逻辑电路作 一定的简化——Minimal cost apporach 对比2：Unused States Treatment Unused States Treatment 26 Output-Coded State Assignment z输出简化, 例如 可以证明，最简“或与 式”只需5项，较“与或 式”需16项来得简单 1 14 3 2 1 2 4 31 2 1 3 421 321 4 321 4321 4321 ( ) ( ) ( ) ( ) ( ) n ERR L G G G LL G G G LLL G G G LLLL G G G L L L L ERR G G G G + =⋅ + + +⋅⋅ + + +⋅ ⋅ ⋅ + + +⋅ ⋅ ⋅⋅ + + +⋅⋅⋅⋅ ⋅ + + + 对比2：Unused States Treatment Unused States Treatment 27 VHDL for the Guessing Game Machine Library IEEE; Use IEEE.std_logic_1164.all; Entity Vggame is Port ( Clock, Reset, G1, G2, G3, G4 : in STD_LOGIC; L1, L2, L3, L4, Err : out STD_LOGIC ); End; Architecture Vggame_arch of Vggame is Type Sreg_type is (S1, S2, S3, S4, SOK, SERR); signal Sreg: Sreg_type; Begin L1 If G2='1' or G3='1' or G4='1' then Sreg If G1='1' or G3='1' or G4='1' then Sreg If G1='1' or G2='1' or G4='1' then Sreg If G1='1' or G2='1' or G3='1' then Sreg If G1='0' and G2='0' and G3='0' and G4='0' then Sreg Sreg <= S1; End case; End If; End If; End process; End Vggame_arch; SErr S1 S2 S3 S4 G1 ’ .G2’.G3’.G4’ G1+G3+G4 G1+G2+G4 G1+G2+G3 G2+G3+G4 G1 ’ .G2’.G3’.G4’ G1 ’ .G2’.G3’.G4’ G1 ’ .G2’.G3’.G4’ G1 ’ .G2’.G3’.G4’ SOK G1 ’ .G2.G3’.G4’ G1 ’ .G2’.G3.G4’ G1 ’ .G2’.G3’.G4 G1.G2’.G3’.G4’ G1+G2+ G3+G4 G1 ’ .G2’.G3’.G4’ SErr S1 S2 S3 S4 G1 ’ .G2’.G3’.G4’ G1+G3+G4 G1+G2+G4 G1+G2+G3 G2+G3+G4 G1 ’ .G2’.G3’.G4’ G1 ’ .G2’.G3’.G4’ G1 ’ .G2’.G3’.G4’ G1 ’ .G2’.G3’.G4’ SOK G1 ’ .G2.G3’.G4’ G1 ’ .G2’.G3.G4’ G1 ’ .G2’.G3’.G4 G1.G2’.G3’.G4’ G1+G2+ G3+G4 G1 ’ .G2’.G3’.G4’ VHDL for the Guessing Game Machine 29 Guessing Game Noting zThe original guessing game is easy to win after a minute of practice because the lamps cycle at a very consistent rate of 4Hz zTo make it more challenging, we can double or triple the clock speed but allow the lamps to stay in each state for a random length of time zThe user truly must guess whether a given lamp will stay on long enough for the corresponding pushbutton to be pressed zAdd an enable input, which is driven by the output of a pseudorandom sequence generator, a Linear Feedback Shift Register (LFSR)
e.g. 3 Traffic Light Controller+ 5.3 Sequential Logic DesignA18 Digital Design: 8.1: 8.8: 8.9 Timing Diagrams Specifications Synchronizer Failure and Metastability o Traffic sensors and signals in an intersection. sunnyvale, California 5.3 Timing Diagrams Specifications 5.3 Timing diagrams ◆ Timing Diagram ◆ Set-up time margin XXXXXXXX XXX XXXXXXXX ∝ XXXXXXXXXXX Flip-Flop XXXXXXXXXXXXXX Set-up time margin t-td(max -tomb(max tsu, must be greate Timing Diagrams Impediments to Sync. Design ◆ Hold time margin ◆ Clock skew CLOCK tpd(Min)+comb(Min -th-tskew(max) >0 Q1 XXXXXXXX XXXXXXXXXXXXX Hold time margin tpd(Min +comb(Min th, must be greater than A long slow path: skew 5
5 30 e.g.3 Traffic Light Controller自学 Traffic sensors and signals in an intersection, Sunnyvale, California 40 5.3 Sequential Logic DesignA18 Digital Design: 8.1; 8.8; 8.9 z Timing Diagrams & Specifications z Impediments to Synchronous Design z Synchronizer Failure and Metastability 41 5.3 Timing Diagrams & Specifications Timing Diagram tclk tsu th tcomb tpd tpd CLOCK Flip-Flop outputs Combinational outputs Flip-Flop Inputs 42 5.3 Timing Diagrams & Specifications Set-up time margin z Set-up time margin tclk-tpd(max)-tcomb(max)-tsu , must be greater than 0 tclk Setup-time margin tsu th tcomb tpd tpd CLOCK Flip-Flop outputs Combinational outputs Flip-Flop Inputs 43 Timing Diagrams Hold time margin z Hold time margin tpd(Min)+tcomb(Min)-th , must be greater than 0 Hold-time margin CLOCK tpd Flip-Flop outputs Combinational outputs Flip-Flop Inputs tclk tsu th tcomb tpd 45 Impediments to Sync. Design* Clock Skew In CP D Q D Q A B Q1 Q2 A long slow path: tskew tpd(Min)+tcomb(Min)-th -tskew(max) >0 tpd(Min)+tcomb(Min)-th>0 Comb
Buffering the clock Buffering the clock ◆ Buffering ◆ Clock tree All in same IC package Even this may produce excessive clock skew if one clock is loaded much more heavily than the othe Transitions on the more heavily loaded clock appear to CLK1 CLK1 ries to balance the loads on multiple clocks CLK2 CLK2 CLS CLK1 Controllable Clock Skew CLK3 Gating the clock DFF with Gated Clock O How not to gate the clock CLK. GCL Simple-minded circuit CLKEN CLK o74X3778-bit register with gated clock elf EN is asserted at the rising edge of the clock Timing diagram then the DFFs are loaded from the data inputs GCLK e Otherwise, they retain their present values Synchronizer Synchronizer Failure° ◆同步器用于同步异步输入 ◆若在同步器输出仍处于亚稳态时使用该信号,将 产生难以预料的结果,称 Synchronizer Failure SYNCIN ASYNCIN ASYNCIN asynchronous input) CLOCK CLOCK
6 46 Buffering the clock Buffering Excessive Clock skew Controllable Clock Skew CLK CLK CLK1 CLK2 CLK CLK1 CLK2 CLK3 All in same IC package 47 Buffering the clock Clock Tree z Even this may produce excessive clock skew if one clock is loaded much more heavily than the other z Transitions on the more heavily loaded clock appear to occur later z Tries to balance the loads on multiple clocks CLK CLK1 CLK2 CLK3 All in same IC package 48 Gating the clock How not to gate the clock Simple-minded circuit CLK GCLK CLKEN CLK GCLK CLKEN Timing diagram 50 DFF with Gated Clock 74X377 8-bit register with gated clock zIf EN is asserted at the rising edge of the clock, then the DFFs are loaded from the data inputs zOtherwise，they retain their present values D Q 8D CLK EN Q 8Q 51 Synchronizer 同步器用于同步异步输入 52 Synchronizer FailureC 若在同步器输出仍处于亚稳态时使用该信号，将 产生难以预料的结果，称Synchronizer Failure
Metastability Timing Diagrams specifications ◆ Metastability Resolution Time:不引起同步器 ◆ Timing Diagram 故障前提下,从时钟跳变时刻起,允许输出处 于亚稳态的最大时间L ◆例如:有效的 Metastability Resolution Time XXXXXX ls - omb -14 tton Flip-Flop XXXXXX tsu =已 Synchronizer Failure Metastability ◆若1个系统在同步器输出仍处于亚稳态时使用该信 ◆等待“多久”才算“久”? 号,将产生难以预料的结果 ●平均故障时间MTBF ◆该现象称为 Synchronizer Failure ◆同步器的平均故障时间 ●理论上亚稳态停留时间随机,其概率随时间指数下降 MTBF()=exp(l/r) ●亚稳态的避免方法是确保使用之前,已等待“足够长”的 ●∫是时钟频率,a是触发器异步输入每秒变化次数 T和r表示常数,由器件电气特性决定 For a typical 74LS74, To-0.4s, r-1.Sns,I,=20ns MTBF(80ns)=xpS 23-3.6.10s if/=10MH:a=10 Metastability One Problem ◆同步器的平均故障时间 ◆ Metastability能否消除 ●能消除 MTBF(L) T·f ●不能消除 ●关于有些制造商,将t的起始点定义为从时 ●正确答案: While the probability of synchronizer 钟跳变时刻延迟t之后的时间 failure can be made small. it can never be eliminated O Reference: Metastability considerations(www as long as there are asynchronous inputs xilinx. com, Xapp077, 1997) ◆多数教材阐述 Metastability现象 7
7 53 Metastability Metastability Resolution Time：不引起同步器 故障前提下, 从时钟跳变时刻起，允许输出处 于亚稳态的最大时间tr 例如：有效的Metastability Resolution Time r clk comb t p se u t =− − tt t 54 Timing Diagrams & Specifications Timing Diagram CLOCK Combinational outputs Flip-Flop Inputs tclk tsu th tcomb tr tr 55 Synchronizer Failure 若1个系统在同步器输出仍处于亚稳态时使用该信 号，将产生难以预料的结果 该现象称为Synchronizer Failure z 理论上亚稳态停留时间随机，其概率随时间指数下降 z 亚稳态的避免方法是确保使用之前，已等待“足够长”的 时间 56 Metastability 等待“多久” 才算 “久” ？ z 平均故障时间MTBF 同步器的平均故障时间 z f 是时钟频率，a 是触发器异步输入每秒变化次数 z T0 和τ 表示常数，由器件电气特性决定 z For a typical 74LS74， T0 =0.4s，τ =1.5ns，ts=20ns 0 exp( ) MTBF( ) r r t τ T f t a = ⋅ ⋅ 5 if 10 10 f MHz a = = 5 if 16 10 f MHz a = = 57 Metastability 同步器的平均故障时间 z关于tr——有些制造商，将tr的起始点定义为从时 钟跳变时刻延迟tffpd之后的时间 Reference : Metastability considerations(www. xilinx.com, Xapp077, 1997) 多数教材阐述Metastablity现象 0 exp( ) MTBF( ) r r t τ T f t a = ⋅ ⋅ 58 One Problem Metastability能否消除？ z能消除 z不能消除 z正确答案：While the probability of synchronizer failure can be made small, it can never be eliminated as long as there are asynchronous inputs
Recommended Synchronizer Better Synchronizer: 1 O Recommended Synchronizer ◆提高MTBF的方法1MTBF()sexp/r) 增加,:=a+tams-t,选用快速触发器减小ln 增加 ●bm=0,最大化的同步器 ●减小τ:快速触发器 Better Synchronizer: 2 Better Synchronizer: 2 ◆ Multiple-cycle synchronizer t,=N·tak- Multiple-cycle synchronizer ● Synchronizer时钟频率ψ,MTBF个 Synchronizer时钟频率↓,MTBF个 O Multiple-cycle synchronizer o Multiple-cycle synchronizer with deskewing Cascaded Synchronizers o Cascaded Synchronizers Better Synchronizer: 2 Metastable-Hardened Flip-Flops +心 o Multiple-Cycle Synchronize L的计算? ◆ Multiple- cycle synch with deskewing cAscaded Synchronize o74AS4374 was similar to 74AS374 ●同一时钟驱动,N个触发器发生故障的概率为P,其中P为 Each individual flip- fiop was replaced with a pair of flip-flops 一个触发器发生错误的概率,标准方法是至少两个触发器 .=m4
8 59 Recommended Synchronizer Recommended Synchronizer Recommended Synchronizer z增加tr : tr = tclk-tcomb-tsu，选用快速触发器减小 tsu ztcomb(Min)=0，tr 最大化的同步器 60 Better Synchronizer: 1 提高MTBF的方法1 z增加tr z减小τ：快速触发器 0 exp( ) MTBF( ) r r t τ t T fa = ⋅ ⋅ 61 Better Synchronizer: 2 Better Synchronizer: 2 Multiple-cycle synchronizer z Synchronizer时钟频率È，MTBFÇ Multiple-cycle synchronizer Cascaded Synchronizers r clk setup t Nt t =⋅ − 62 Better Synchronizer: 2 Multiple-cycle synchronizer z Synchronizer时钟频率È，MTBFÇ Multiple-cycle synchronizer with deskewing Cascaded Synchronizers 63 Better Synchronizer: 2 Better Synchronizer: 2 Multiple-Cycle Synchronizer Multiple-cycle synchronizer with deskewing Cascaded Synchronizers z 同一时钟驱动，N个触发器发生故障的概率为PN，其中P为 一个触发器发生错误的概率，标准方法是至少两个触发器 tr的计算？ r clk setup t nt t =⋅ − r clk setup ⇒ =⋅ −⋅ t nt nt 64 Metastable-Hardened Flip-Flops 74AS4374 was similar to 74AS374 z Each individual flip-flop was replaced with a pair of flip-flops
