Philips Semiconductors ation USB interface device with parallel bus PDIUSBD12 BLOCK DIAGRAM 6 MHz UPSTREAM INTEGRATED BIT CLOCK 1.5k9 ANALOG PHILIPS MEMORY VOLTAGE REGULATOR NOTE. This is a conceptual block diagram and does not include each individual signa Analog Transceiver SoftconnectTw The integrated transceiver interfaces directly to the USB cables The connection to the USB is accomplished by bringing D+(for hrough termination resistors high-speed USB device) high through a 1.5 kQ pull-up resistor. In Voltage Regulator the PDIUSBD12, the 1.5 k@2 pull-up resistor is integrated on-chip and is not connected to Vcc by default. The connection is A 3. 3v regulator is integrated on-chip to supply og established through a command sent by the external/system transceiver. This voltage is also provided as ar connect to microcontroller. This allows the system microcontroller to complete the external 1.5 k]2 pull-up resistor. Altematively, USBD12 its initialization sequence before deciding to establish connection to provides Soft Connectm technology with integrated 1.5 k@2 pull-up the USB. Re-initialization of the usb bus connection can also be performed without requiring to pull out the cable PLL The PDIUSBD12 will check for USB VBUS availability before the A 6 MHz to 48 MHz clock multiplier PLL (Phase-Locked Loop) is connection can be established. VBUS sensing is provided through integrated on-chip. This allows for the use of low-cost 6 MHz crystal EOT N pin. See the pin description for details. Sharing of VBUs EMI is also minimized due to the lower frequency crystal. No sensing and EOT N can be easily accomplished by using VBUS external components are needed for the operation of the PLL. voltage as the pull up voltage for the normally open-drain output of the dma controller pir ecove It should be noted that the tolerance of the intemal resistors is The bit clock recovery circuit recovers the clock from the incomin k ugher(25%)than that specified by the USB specification(5%) USB data stream using 4X over-sampling principle. It is able to track jitter and frequency drift specified by the USB specification. However, the overall VsE voltage specification for the connection can still be met with good margin. The decision to make sure of this Philips Serial Interface Engine(PSI) feature lies with the users he Philips SIE implements the full USB protocol layer. It is completely hardwired for speed and needs no firmware intervention SoftconnectM is a patent pending technology from Philips The functions of this block include: synchronization patten recognition, parallel/serial conversion, bit stuffing/de-stuffing, CRC checking/generation, PID verification/generation, address ecognition, and handsPhilips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 1999 Jan 08 3 BLOCK DIAGRAM PARALLEL AND DMA INTERFACE ANALOG TX/RX PHILIPS SIE INTEGRATED RAM BIT CLOCK RECOVERY MEMORY MANAGEMENT UNIT 6 MHz D+ D– UPSTREAM PORT PLL SoftConnect D+ 3.3V 1.5k
SV00859 VOLTAGE REGULATOR NOTE: * This is a conceptual block diagram and does not include each individual signal. Analog Transceiver The integrated transceiver interfaces directly to the USB cables through termination resistors. Voltage Regulator A 3.3V regulator is integrated on-chip to supply the analog transceiver. This voltage is also provided as an output to connect to the external 1.5 kΩ pull-up resistor. Alternatively, the PDIUSBD12 provides SoftConnect technology with integrated 1.5 kΩ pull-up resistor. PLL A 6 MHz to 48 MHz clock multiplier PLL (Phase-Locked Loop) is integrated on-chip. This allows for the use of low-cost 6 MHz crystal. EMI is also minimized due to the lower frequency crystal. No external components are needed for the operation of the PLL. Bit Clock Recovery The bit clock recovery circuit recovers the clock from the incoming USB data stream using 4X over-sampling principle. It is able to track jitter and frequency drift specified by the USB specification. Philips Serial Interface Engine (PSIE) The Philips SIE implements the full USB protocol layer. It is completely hardwired for speed and needs no firmware intervention. The functions of this block include: synchronization pattern recognition, parallel/serial conversion, bit stuffing/de-stuffing, CRC checking/generation, PID verification/generation, address recognition, and handshake evaluation/generation. SoftConnect The connection to the USB is accomplished by bringing D+ (for high-speed USB device) high through a 1.5 kΩ pull-up resistor. In the PDIUSBD12, the 1.5 kΩ pull-up resistor is integrated on-chip and is not connected to VCC by default. The connection is established through a command sent by the external/system microcontroller. This allows the system microcontroller to complete its initialization sequence before deciding to establish connection to the USB. Re-initialization of the USB bus connection can also be performed without requiring to pull out the cable. The PDIUSBD12 will check for USB VBUS availability before the connection can be established. VBUS sensing is provided through EOT_N pin. See the pin description for details. Sharing of VBUS sensing and EOT_N can be easily accomplished by using VBUS voltage as the pull up voltage for the normally open-drain output of the DMA controller pin. It should be noted that the tolerance of the internal resistors is higher (25%) than that specified by the USB specification (5%). However, the overall VSE voltage specification for the connection can still be met with good margin. The decision to make sure of this feature lies with the users. SoftConnect is a patent pending technology from Philips Semiconductors