例1:设计8-3优先权编码器 LIBRARY IEEE USE IEEE STD LOGIC 1164.ALL: enTiTY bmg83 IS PORT D IN STD LOGIC VECOR(7 DOWNTO 0); 二编码器设计 OUT STD LOGIC VECTOR(2 DOWNTO 0)); ENd bmg83 aRChItECtURE behavior OF bmg83 Is BEGIN PROCESS) BEGIN IFD(7=0 THEN Y<=“000”; ELSIF D(6=0 THEN Y<=“001”; ELSIF D(5)=“0 THEN Y<=“010”; 该描述具 ELSIF D(4)=0 THEN Y<=“011”; 有优先级 ELSIF D(3)=“0 THEN Y<=“100 ELSIF D(2=0 THEN Y<=“101”; ELSIF D(1)=0 THEN Y<=“110”; ELSIF D(0)=0 THEN Y<=“11”; ELSY<=“XXX”; END PROCESS END behavior;二 编 码 器 设 计 例1：设计8－3优先权编码器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY bmq83 IS PORT( D: IN STD_LOGIC_VECOR(7 DOWNTO 0); Y: OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); END bmq83; ARCHITECTURE behavior OF bmq83 IS BEGIN PROCESS(D) BEGIN IF D(7)=‘0’ THEN Y<=“000”; ELSIF D(6)=‘0’ THEN Y<=“001”; ELSIF D(5)=‘0’ THEN Y<=“010”; ELSIF D(4)=‘0’ THEN Y<=“011”; ELSIF D(3)=‘0’ THEN Y<=“100”; ELSIF D(2)=‘0’ THEN Y<=“101”; ELSIF D(1)=‘0’ THEN Y<=“110”; ELSIF D(0)=‘0’ THEN Y<=“111”; ELS Y<=“XXX”; END PROCESS; END behavior; 该描述具 有优先级