Philips Semiconductors ation USB interface device with parallel bus PDIUSBD12 DMA TRANSFER Direct Memory Address(DMA) allows an efficient transfer of a block transfer(bulk and interrupt), the buffer needs to be completely filled of data between the host and the local shared memory. Using a up by the DMA write operation before the data is sent to the host. controller. data transfer between the pdiusbd12 main The only exception is at the end of DMA transfer when the reception oint(endpoint 2)and the local shared memory can happen of EOT N will stop DMA write operation and the buffer content will autonomously without local CPU intervention. be sent to the host on the next iN token Preceding any DMA transfer, the local CPU receives from the host For isochronous transfer the local cpu and dma controller has to the necessary setup information and programs the DMA controller guarantee that they are able to sink or source the maximum packet accordingly. Typically, the DMA controller is setup for demand size in one USB frame(1 ms) transfer mode and the byte count register and the address counter are programmed with the right values. In this mode, transfers occur The assertion of DMACK N will automatically selects the main only when the PDIUSBD12 requests them and terminated when the endpoint(endpoint 2) regardless of the current selected endpoint byte count register reaches zero. After the DMA controller has been The DMA operation of the PDIUSBD12 can be interleaved with programmed, the dMa enable bit of the PDIUSBD12 is set by the normal l/o access to other endpoints local cpu to initiate the transfer DMA operation can be terminated by resetting the DMA enable The PDIUSBD12 can be programmed for single cycle DMA or burst register bit or the assertion of EOT N together with DMACK N and mode DMA In single cycle DMA, the DMREQ is deactivated for either rd n or Wr n every single acknowledgement by the DMACK_N before be for PDIUSBD12 supports DMA transfer in a single address mode and it can also work in dual address mode of the dma controller. In the the number of bursts programmed in the device before retuming single address mode, DMA transfer is done via the DREQ, inactive. This process continues until the PDIUSBD12 receives a DMACK N, EOT N. WR N and Rd N control lines. In the dual DMA termination notice through EOT N. This will generate an interrupt to notify the local CPU that DMA operation is completed. address mode, DMREQ, DMACK N and EoT N are Not usec instead CS_N, WR N and RD_N control signals are used. The vO For DMA read operation, the dMREQ will only be activated mode Transfer Protocol of pdiusbd 12 needs to be followed the whenever the buffer is full signifying that the host has successfully source of the DMAC is accessed during the read cycle, and the transferred a packet to the PDIUSBD12. With the double buffering destination accessed during the write cycle. Transfer needs to be scheme, the host can start filling up the second buffer while the first done in two separate bus cycles, storing the data temporarly in the buffer is being read out. This parallel processing increases effective DMAC oughput. For the case when the host does not fill up the buffer ompletely (less than 64 bytes or 128 bytes for single direction ISo ENDPOINT DESCRIPTION configuration), the DMREQ will be deactivated at the last byte of the The PDIUSBD12 endpoints are generic enough to be used by buffer regardless of the current DMA burst count. It will be asserted various device classes ranging from Imaging, Printer, Mass Storage again on the next packet with a refreshed DMA burst count. and Communication device classes. The PDIUSBD12 endpoints can Similarly, for DMA write operation, the DMRI be configured for 4 modes depending on the"Set Mode" command whenever the buffer is not full. when the but The 4 modes are: packet is sent over to the host on the next IN Mode 0(Non-ISO Mode): no Isochronous transfer be reactivated if the transfer was successful. also the double Mode 1(ISO-OUT Mode ): Isochronous output only buffering scheme here will improve throughput For non-isochronous Mode 2(ISo-IN Mode): Isochronous input only tra Mode 3(So-IO Mode) sychronous input and ouPhilips Semiconductors Product specification USB interface device with parallel bus PDIUSBD12 1999 Jan 08 5 DMA TRANSFER Direct Memory Address (DMA) allows an efficient transfer of a block of data between the host and the local shared memory. Using a DMA controller, data transfer between the PDIUSBD12 main endpoint (endpoint 2) and the local shared memory can happen autonomously without local CPU intervention. Preceding any DMA transfer, the local CPU receives from the host the necessary setup information and programs the DMA controller accordingly. Typically, the DMA controller is setup for demand transfer mode and the byte count register and the address counter are programmed with the right values. In this mode, transfers occur only when the PDIUSBD12 requests them and terminated when the byte count register reaches zero. After the DMA controller has been programmed, the DMA enable bit of the PDIUSBD12 is set by the local CPU to initiate the transfer. The PDIUSBD12 can be programmed for single cycle DMA or burst mode DMA. In single cycle DMA, the DMREQ is deactivated for every single acknowledgement by the DMACK_N before being asserted again. In burst mode DMA, the DMREQ is held active for the number of bursts programmed in the device before returning inactive. This process continues until the PDIUSBD12 receives a DMA termination notice through EOT_N. This will generate an interrupt to notify the local CPU that DMA operation is completed. For DMA read operation, the DMREQ will only be activated whenever the buffer is full signifying that the host has successfully transferred a packet to the PDIUSBD12. With the double buffering scheme, the host can start filling up the second buffer while the first buffer is being read out. This parallel processing increases effective throughput. For the case when the host does not fill up the buffer completely (less than 64 bytes or 128 bytes for single direction ISO configuration), the DMREQ will be deactivated at the last byte of the buffer regardless of the current DMA burst count. It will be asserted again on the next packet with a refreshed DMA burst count. Similarly, for DMA write operation, the DMREQ remains active whenever the buffer is not full. When the buffer is filled up, the packet is sent over to the host on the next IN token and DMREQ will be reactivated if the transfer was successful. Also, the double buffering scheme here will improve throughput. For non-isochronous transfer (bulk and interrupt), the buffer needs to be completely filled up by the DMA write operation before the data is sent to the host. The only exception is at the end of DMA transfer when the reception of EOT_N will stop DMA write operation and the buffer content will be sent to the host on the next IN token. For isochronous transfer, the local CPU and DMA controller has to guarantee that they are able to sink or source the maximum packet size in one USB frame (1 ms). The assertion of DMACK_N will automatically selects the main endpoint (endpoint 2) regardless of the current selected endpoint. The DMA operation of the PDIUSBD12 can be interleaved with normal I/O access to other endpoints. DMA operation can be terminated by resetting the DMA enable register bit or the assertion of EOT_N together with DMACK_N and either RD_N or WR_N. PDIUSBD12 supports DMA transfer in a single address mode and it can also work in dual address mode of the DMA controller. In the single address mode, DMA transfer is done via the DREQ, DMACK_N, EOT_N, WR_N and RD_N control lines. In the dual address mode, DMREQ, DMACK_N and EOT_N are NOT used, instead CS_N, WR_N and RD_N control signals are used. The I/O mode Transfer Protocol of PDIUSBD12 needs to be followed. The source of the DMAC is accessed during the read cycle, and the destination accessed during the write cycle. Transfer needs to be done in two separate bus cycles, storing the data temporarily in the DMAC. ENDPOINT DESCRIPTION The PDIUSBD12 endpoints are generic enough to be used by various device classes ranging from Imaging, Printer, Mass Storage and Communication device classes. The PDIUSBD12 endpoints can be configured for 4 modes depending on the “Set Mode” command. The 4 modes are: Mode 0 (Non-ISO Mode): no Isochronous transfer Mode 1 (ISO-OUT Mode): Isochronous output only transfer Mode 2 (ISO-IN Mode): Isochronous input only transfer Mode 3 (ISO-IO Mode): Isochronous input and output transfer