AegaWizard Plug-In Manager ALTSYNCRAM [page 7 of 10] ☒ Mcre Options. 厂8 Cancal <Baok Ned Frith Figure 3.Configuring input and output ports on the altsyncram LPM. 3.Compile the circuit.Observe in the Compilation Report that the Ouartus II Compiler uses 256 bits in one of the M4K memory blocks to implement the RAM circuit. 4.Simulate the behavior ofyour circuit and ensure that you can read and write data in the memory. PartII plays 1.Make a new Quartus II project which will be used to implement the desired circuit on the DE2 board. 2QDsR e as the Write signal and use i on HEXS and HEX.and show the data read out of the memory on HEXI and HEX0. 3.Test your circuit and make sure that all 32 locations can be loaded properly. Part IlI Instead of directly in ating the lpm module on h ture in the VHDL code.In a VHDLs array.A 32x8 array,which has 32 words with8 bits per word,can be declared by the statements TYPE mem Is ArrAY(O TO 31)OF STDLOGIC VECTOR(7 DOWNTO O): SIGNAL memoryarray:mem;Figure 3. Configuring input and output ports on the altsyncram LPM. 3. Compile the circuit. Observe in the Compilation Report that the Quartus II Compiler uses 256 bits in one of the M4K memory blocks to implement the RAM circuit. 4. Simulate the behavior of your circuit and ensure that you can read and write data in the memory. Part II Now, we want to realize the memory circuit in the FPGA on the DE2 board, and use toggle switches to load some data into the created memory. We also want to display the contents of the RAM on the 7-segment displays. 1. Make a new Quartus II project which will be used to implement the desired circuit on the DE2 board. 2. Create another VHDL file that instantiates the ramlpm module and that includes the required input and output pins on the DE2 board. Use toggle switches SW7−0 to input a byte of data into the RAM location identified by a 5-bit address specified with toggle switches SW15−11. Use SW17 as the Write signal and use KEY0 as the Clock input. Display the value of the Write signal on LEDG0. Show the address value on the 7-segment displays HEX7 and HEX6, show the data being input to the memory on HEX5 and HEX4, and show the data read out of the memory on HEX1 and HEX0. 3. Test your circuit and make sure that all 32 locations can be loaded properly. Part III Instead of directly instantiating the LPM module, we can implement the required memory by specifying its struc￾ture in the VHDL code. In a VHDL-specified design it is possible to define the memory as a multidimensional array. A 32 x 8 array, which has 32 words with 8 bits per word, can be declared by the statements TYPE mem IS ARRAY(0 TO 31) OF STD LOGIC VECTOR(7 DOWNTO 0); SIGNAL memory array : mem; 3