the fiin-fl be used.One is to use an LPM module from the Library of Parameterized Modules,as we saw in Part I.The other sto dctine the memory rqurmen byuin suabe style of this maybentp a m the l II Help shows lelp fo "in d men Perform the following steps: 1.Create a new project which will be used to implement the desired circuit on the DE2 board. 2.Write a VHDL file that provides the necessary functionality.including the ability to load the RAMand read its contents as done in Part II. 3.Assign the pins on the FPGA to connect to the switches and the 7-segment displays. 4.Compile the circuit and download it into the FPGA chip. 5.t the functionality of your design by applying some inputs and observing the output.Deseribe any erences you observe in comparison to the circuit from Part I PartIV The DE2 board includes an SRAM chip,called IS61LV25616AL-10,which is a static RAM having a capacity Name Purpose Chip enable-asserted low during all SRAM operations can be assered ow during ony read operations,or during all operations B ed lou the byte of an address Table 1.SRAM control inputs. The he chin is described in i of modes of operation of the memory and lists many timing parameters related to its use his exercise mple operating mode s to always assert(set ntrol inp nto this mode are appears on Aand the WE input is not asserted.The memory places valid data on the I/port after the address access delay,t.When the read cycle ends because of a change in the address value,the output data remains valid for the ouput hold time,toA. In the Cyclone II FPGA, such an array can be implemented either by using the flip-flops that each logic element contains or, more efficiently, by using the M4K blocks. There are two ways of ensuring that the M4K blocks will be used. One is to use an LPM module from the Library of Parameterized Modules, as we saw in Part I. The other is to define the memory requirement by using a suitable style of VHDL code from which the Quartus II compiler can infer that a memory block should be used. Quartus II Help shows how this may be done with examples of VHDL code (search in the Help for “Inferred memory”). Perform the following steps: 1. Create a new project which will be used to implement the desired circuit on the DE2 board. 2. Write a VHDL file that provides the necessary functionality, including the ability to load the RAM and read its contents as done in Part II. 3. Assign the pins on the FPGA to connect to the switches and the 7-segment displays. 4. Compile the circuit and download it into the FPGA chip. 5. Test the functionality of your design by applying some inputs and observing the output. Describe any differences you observe in comparison to the circuit from Part II. Part IV The DE2 board includes an SRAM chip, called IS61LV25616AL-10, which is a static RAM having a capacity of 256K 16-bit words. The SRAM interface consists of an 18-bit address port, A 17−0, and a 16-bit bidirectional data port, I/O15−0. It also has several control inputs, CE, OE, W E, UB, and LB, which are described in Table 1. Name Purpose CE Chip enable−asserted low during all SRAM operations OE Output enable−can be asserted low during only read operations, or during all operations W E Write enable−asserted low during a write operation UB Upper byte−asserted low to read or write the upper byte of an address LB Lower byte−asserted low to read or write the lower byte of an address Table 1. SRAM control inputs. The operation of the IS61LV25616AL chip is described in its data sheet, which can obtained from the DE2 System CD that is included with the DE2 board, or by performing an Internet search. The data sheet describes a number of modes of operation of the memory and lists many timing parameters related to its use. For the purposes of this exercise a simple operating mode is to always assert (set to 0) the control inputs CE, OE, UB, and LB, and then to control reading and writing of the memory by using only the W E input. Simplified timing diagrams that correspond to this mode are given in Figure 4. Part (a) shows a read cycle, which begins when a valid address appears on A17−0 and the W E input is not asserted. The memory places valid data on the I/O15−0 port after the address access delay, tAA. When the read cycle ends because of a change in the address value, the output data remains valid for the output hold time, tOHA. 4