K述列 4.1多路选择器VHDL指述 4.1.12选1多路选择器的ⅤHDL描述 例42】 ENTTY mU%21a工s PoR(a,b:工NBrT; s:工NB工T; Y:OUB工T) END ENT工 Y mux21a; ARCHITECTURE one OF mux21a IS sIGNaL, d,e B工T; BEGIN d < a AND (NOT S); e <=b AND s y < dore i END ARCHITECTUREoneKX 康芯科技 4.1 多路选择器VHDL描述 4.1.1 2选1多路选择器的VHDL描述 【例4-2】 ENTITY mux21a IS PORT ( a, b : IN BIT; s : IN BIT; y : OUT BIT ); END ENTITY mux21a; ARCHITECTURE one OF mux21a IS SIGNAL d,e : BIT; BEGIN d <= a AND (NOT S) ; e <= b AND s ; y <= d OR e ; END ARCHITECTURE one ;