1.Make a new Quartus lI project and write VHDL code that describes the circuit in Figure 1.Use the circuit structure in Figure atodescribe your adder. 2.Include the required input and output ports in your project to implement the adder circuit on the DE2 board. Connect the inputs A and B to switches SW1s-s and SW7.respectively.Use KEYo as an active-low s res input,and us KEY as a manual clocl input.Display the sum outputs of the adder on nal value of s should appear on HEXI-0. 3.Compile your code and use timing simulation to verify the correct operation of the circuit.Once the sim DE2 board and test it by using different values of A delay? PartⅡ and displays as described for Part I. 1.Simulate vour adder/subtractor circuit to show that it functions p roperly.and then download itonto the DE2 board and test it by using different switch settings. 2.Open the Quartus II Compilation Report and examine the results reported by the Timing Analyzer.What is the fmax of your circuit?What is the longest path in the circuit in terms of delay PartI me or n the rogram sectio of Al module in your VHDL code,compile the project and use the Quartus II Chip Editor tool to examine some of the details of the implemented circuit One way to examine the adder subcircuit using the Chip Editor tool is illustrated in Figure 2.In the Quartu right-ick the chy that ents the lpm add8 the co Thi te opens the Chip E tor windo logic element operty Editor window displayed in Figure 4.In the box labeled ws you1. Make a new Quartus II project and write VHDL code that describes the circuit in Figure 1b. Use the circuit structure in Figure 1a to describe your adder. 2. Include the required input and output ports in your project to implement the adder circuit on the DE2 board. Connect the inputs A and B to switches SW15−8 and SW7−0, respectively. Use KEY0 as an active-low asynchronous reset input, and use KEY1 as a manual clock input. Display the sum outputs of the adder on the red LEDR7−0 lights and display the overflow output on the green LEDG8 light. The hexadecimal values of A and B should be shown on the displays HEX7-6 and HEX5-4, and the hexadecimal value of S should appear on HEX1-0. 3. Compile your code and use timing simulation to verify the correct operation of the circuit. Once the sim￾ulation works properly, download the circuit onto the DE2 board and test it by using different values of A and B. Be sure to check for proper functionality of the Overflow output. 4. Open the Quartus II Compilation Report and examine the results reported by the Timing Analyzer. What is the maximum operating frequency, fmax, of your circuit? What is the longest path in the circuit in terms of delay? Part II Modify your circuit from Part I so that it can perform both addition and subtraction of eight-bit numbers. Use switch SW16 to specify whether addition or subtraction should be performed. Connect the other switches, lights, and displays as described for Part I. 1. Simulate your adder/subtractor circuit to show that it functions properly, and then download it onto the DE2 board and test it by using different switch settings. 2. Open the Quartus II Compilation Report and examine the results reported by the Timing Analyzer. What is the fmax of your circuit? What is the longest path in the circuit in terms of delay? Part III Repeat Part I using the predefined adder circuit called lpm add sub, instead of your ripple-carry adder structure from Figure 1. The lpm add sub module can be found in Altera’s library of parameterized modules (LPMs), which is provided as part of the Quartus II system. The procedure for using these predefined modules in Quartus II projects is described in the tutorial Using Library Modules in VHDL Designs, which is available on the DE2 System CD and in the University Program section of Altera’s web site. 1. Configure the lpm add sub module so that it performs only addition, to make the functionality comparable to Part I. Store your configuration of the lpm add sub module in the file lpm add8.v. After instantiating this module in your VHDL code, compile the project and use the Quartus II Chip Editor tool to examine some of the details of the implemented circuit. One way to examine the adder subcircuit using the Chip Editor tool is illustrated in Figure 2. In the Quartus II Project Navigator window right-click on the part of your circuit hierarchy that represents the lpm add8 subcircuit, and select the command Locate > Locate in Chip Editor. This opens the Chip Editor window shown in Figure 3. The logic elements in the Cyclone II FPGA that are used to implement the adder are highlighted in blue in the Chip Editor tool. Position your mouse pointer over any of these logic elements and double-click to open the Resource Property Editor window displayed in Figure 4. In the box labeled Node name you can select any of the nine logic elements that implement the adder module. The Resource Property Editor allows you to examine the contents of a logic element and to see how one logic element is connected others. 2