课程简介-经典的并发模型：Pipeline（4) A five-stage pipelined superscalar processor, capable of issuing two instructions per cycle.It can have two instructions in each stage of the pipeline,for a total of up to 10 instructions (shown in green)being simultaneously executed.课程简介-经典的并发模型：Pipeline （4） • A five-stage pipelined superscalar processor, capable of issuing two instructions per cycle. It can have two instructions in each stage of the pipeline, for a total of up to 10 instructions (shown in green) being simultaneously executed