课程简介-经典的并发模型：Pipeline（3)》 A canonical five-stage pipeline in a RISC machine (IF Instruction Fetch,ID Instruction Decode,EX Execute,MEM Memory access,WB Register write back) IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB课程简介-经典的并发模型：Pipeline （3） • A canonical five-stage pipeline in a RISC machine (IF = Instruction Fetch, ID = Instruction Decode, EX = Execute, MEM = Memory access, WB = Register write back)