Vol.32,No.2 Journal of Semiconductors February 2011 A 10-bit 80-MS/s opamp-sharing pipelined ADC with a switch-embedded dual-input MDAC* Yin Rui((尹容)，2，Liao Youchun(廖友春)2，Zhang Wei(张卫)'，and Tang Zhangwen((唐长文)l,t 1ASIC&System State Key Laboratory,Fudan University,Shanghai 201203,China 2Ratio Microelectronics Co.,Ltd,Shanghai 200433,China Abstract:A 10-bit 80-MS/s opamp-sharing pipelined ADC is implemented in a 0.18-um CMOS.An opamp- sharing MDAC with a switch-embedded dual-input opamp is proposed to eliminate the non-resetting and successive-stage crosstalk problems observed in the conventional opamp-sharing technique.The ADC achieves a peak SNDR of 60.1 dB(ENOB =9.69 bits)and a peak SFDR of 76 dB,while maintaining more than 9.6 ENOB for the full Nyquist input bandwidth.The core area of the ADC is 1.1 mm2 and the chip consumes 28 mW with a 1.8 V power supply. Key words:pipelined ADC;opamp-sharing;low power,switch-embedded;dual-input MDAC D0:10.1088/1674-4926/32/2/025006 EEACC:1205:1265H:1280 sharing pipelined ADC utilizing a switch-embedded dual-input 1.Introduction MDAC that achieves a very high accuracy Applications used in many electronic systems,such as 2.Conventional opamp-sharing MDAC video decoder and a high-speed wire line and wireless com- munication,require high-resolution low-power Nyquist-rate Although opamp sharing technology can save nearly half analog-to-digital converters (ADCs).The specifications of of the power consumption,it is achieved at the cost of reso- conversion rates higher than 50 MSample/s and signal-to- lution reduction,since the conventional opamp-sharing ADC noise-and-distortion ratio (SNDR)in the range of 50-60 dB has two serious problems.First,because the opamp input sum- are usually required.To meet the applications of the integra- ming node is never reset,every input sample is affected by the tion of on-chip ADCs in the analog front-end with digital signal error voltage stored on the input capacitor due to the previ- processors,low-power ADCs are much preferred.In addition, ous sample.Thus it suffers from the memory effect,which can for the increasingly popular portable amusement,low power be considered as a signal-dependent OTA offset.To avoid consumption is even more crucial for extending the duration memory effects,the OTA inputs can be reset using a short du- of the system powered by a battery.Among many ADC archi- ration third phase.However,this would reduce the time avail- tectures,the pipelined ADC architecture has commonly been able for MDAC stage output settling.Second,there is a poten- employed to optimize speed,resolution.power dissipation and tial crosstalk path between two successive stages caused by the chip area,and has proved to be very efficient in meeting these parasitic capacitors of switches,which are used to implement requirements of high speed,high resolution,and low power opamp sharing.The conventional opamp-sharing MDAC with consumption.The efficiency mainly depends on the"pipeline" parasitic capacitance is shown in Fig.1.The signals in the cur- operation of the ADC stages.Each stage processes data from rent and successive stages,which appear at input nodes of the the previous stage as soon as its output is passed to the next shared opamp,will influence each other through the crosstalk stage for sampling.This means that the pipelined ADC can path.In addition,the opamp-sharing switches also introduce achieve one conversion in each clock cycle.The most efficient charge injection and signal-dependent resistance.These factors method that has been utilized to obtain significant power sav- degrade both the linearity and the signal-to-noise-ratio(SNR). ing is opamp sharing between multiplying digital-to-analogue To alleviate the non-resetting problem,the feedback signal converter(MDAC)stages in pipelined ADCs[1-51.That is be- polarity inverting(FSPI)is used to alternate the signal polar- cause the signal amplification in each MDAC stage is in al- ity,but it can only reduce the opamp offset by 2/321.To break ternate phases,so the operational transconductance amplifier the crosstalk path,isolation switches are added to tie the para- (OTA)only works in a half clock cycle.Therefore,half of sitic capacitance to ground in the sample phase,the SNDR is the opamps can be removed,leading to nearly 50%power improved only by 1-2 dB,but the added switches increase the reduction.However,the conventional opamp-sharing MDAC series resistance and the charge injection Although opamp has the issues of non-resetting and successive stage crosstalk. current reuse can solve the problems of non-resetting and To overcome these problems,this paper proposes an opamp- crosstalk path by using both NMOS and PMOS input differ- Project supported by the National Natural Science Foundation of China(No.60876019),the National S&T Major Project of China(No. 2009ZX0131-002-003-02),the Shanghai Rising-Star Program (No.09QA1400300),the National Scientists and Engineers Service for Enterprise Program,China(No.2009GJC00046),and the ASIC State-Key Laboratory Funding,China (No.09MS007). Corresponding author.Email:zwtang @fudan.edu.cn Received 12 August 2010,revised manuscript received 14 September 2010 C2011 Chinese Institute of Electronics 025006-1Vol. 32, No. 2 Journal of Semiconductors February 2011 A 10-bit 80-MS/s opamp-sharing pipelined ADC with a switch-embedded dual-input MDAC Yin Rui(尹睿) 1; 2, Liao Youchun(廖友春) 2 , Zhang Wei(张卫) 1 , and Tang Zhangwen(唐长文) 1; Ž 1ASIC & System State Key Laboratory, Fudan University, Shanghai 201203, China 2Ratio Microelectronics Co., Ltd, Shanghai 200433, China Abstract: A 10-bit 80-MS/s opamp-sharing pipelined ADC is implemented in a 0.18-m CMOS. An opamp￾sharing MDAC with a switch-embedded dual-input opamp is proposed to eliminate the non-resetting and successive-stage crosstalk problems observed in the conventional opamp-sharing technique. The ADC achieves a peak SNDR of 60.1 dB (ENOB = 9.69 bits) and a peak SFDR of 76 dB, while maintaining more than 9.6 ENOB for the full Nyquist input bandwidth. The core area of the ADC is 1.1 mm2 and the chip consumes 28 mW with a 1.8 V power supply. Key words: pipelined ADC; opamp-sharing; low power; switch-embedded; dual-input MDAC DOI: 10.1088/1674-4926/32/2/025006 EEACC: 1205; 1265H; 1280 1. Introduction Applications used in many electronic systems, such as video decoder and a high-speed wire line and wireless com￾munication, require high-resolution low-power Nyquist-rate analog-to-digital converters (ADCs). The specifications of conversion rates higher than 50 MSample/s and signal-to￾noise-and-distortion ratio (SNDR) in the range of 50–60 dB are usually required. To meet the applications of the integra￾tion of on-chip ADCs in the analog front-end with digital signal processors, low-power ADCs are much preferred. In addition, for the increasingly popular portable amusement, low power consumption is even more crucial for extending the duration of the system powered by a battery. Among many ADC archi￾tectures, the pipelined ADC architecture has commonly been employed to optimize speed, resolution, power dissipation and chip area, and has proved to be very efficient in meeting these requirements of high speed, high resolution, and low power consumption. The efficiency mainly depends on the “pipeline” operation of the ADC stages. Each stage processes data from the previous stage as soon as its output is passed to the next stage for sampling. This means that the pipelined ADC can achieve one conversion in each clock cycle. The most efficient method that has been utilized to obtain significant power sav￾ing is opamp sharing between multiplying digital-to-analogue converter (MDAC) stages in pipelined ADCsŒ1￾5. That is be￾cause the signal amplification in each MDAC stage is in al￾ternate phases, so the operational transconductance amplifier (OTA) only works in a half clock cycle. Therefore, half of the opamps can be removed, leading to nearly 50% power reduction. However, the conventional opamp-sharing MDAC has the issues of non-resetting and successive stage crosstalk. To overcome these problems, this paper proposes an opamp￾sharing pipelined ADC utilizing a switch-embedded dual-input MDAC that achieves a very high accuracy. 2. Conventional opamp-sharing MDAC Although opamp sharing technology can save nearly half of the power consumption, it is achieved at the cost of reso￾lution reduction, since the conventional opamp-sharing ADC has two serious problems. First, because the opamp input sum￾ming node is never reset, every input sample is affected by the error voltage stored on the input capacitor due to the previ￾ous sample. Thus it suffers from the memory effect, which can be considered as a signal-dependent OTA offsetŒ1. To avoid memory effects, the OTA inputs can be reset using a short du￾ration third phase. However, this would reduce the time avail￾able for MDAC stage output settling. Second, there is a poten￾tial crosstalk path between two successive stages caused by the parasitic capacitors of switches, which are used to implement opamp sharing. The conventional opamp-sharing MDAC with parasitic capacitance is shown in Fig. 1. The signals in the cur￾rent and successive stages, which appear at input nodes of the shared opamp, will influence each other through the crosstalk path. In addition, the opamp-sharing switches also introduce charge injection and signal-dependent resistance. These factors degrade both the linearity and the signal-to-noise-ratio (SNR). To alleviate the non-resetting problem, the feedback signal polarity inverting (FSPI) is used to alternate the signal polar￾ity, but it can only reduce the opamp offset by 2/3Œ2. To break the crosstalk path, isolation switches are added to tie the para￾sitic capacitance to ground in the sample phase, the SNDR is improved only by 1–2 dB, but the added switches increase the series resistance and the charge injectionŒ3. Although opamp current reuse can solve the problems of non-resetting and crosstalk path by using both NMOS and PMOS input differ- * Project supported by the National Natural Science Foundation of China (No. 60876019), the National S&T Major Project of China (No. 2009ZX0131-002-003-02), the Shanghai Rising-Star Program (No. 09QA1400300), the National Scientists and Engineers Service for Enterprise Program, China (No. 2009GJC00046), and the ASIC State-Key Laboratory Funding, China (No. 09MS007). Ž Corresponding author. Email: zwtang@fudan.edu.cn Received 12 August 2010, revised manuscript received 14 September 2010 c 2011 Chinese Institute of Electronics 025006-1