ND MSE FCW MCU DDFS CORE COM FO UD (X Fig.3.Architecture of Quadrature Frequency Synthesizer/Mixer Fig.4.Optimized Architecture of DDFS In this paper,the word length of the phase accumulator is 32 bits and the maximum clock frequency is 200MHz.Thus the minimum frequency resolution is 0.0466Hz.The switching speed between two frequencies is one clock cycle,5ns. ROM 2 -COM Fig.3 is the architecture of the quadrature frequency syn- 32bt LUT thesizer/mixer.which consists of four main modules:direct digital frequency synthesizer,modified Booth multiplier with Wallace adder tree,anti-SINC FIR filter with CSD coefficients 0 and a simple microcontroller.Direct digital frequency synthesizer employs one-eighth sine waveform compression Fig.5.Modulation Capabilities algorithms to achieve high frequency resolution and high bandwidth.12-bit x 12-bit multipliers adopt modified Booth and that of the fine ROM is 4 bits.Thus,214X12 sine samples encode and Wal-lace adder tree to improve the speed of are compressed into 28 X 11 coarse samples and 2%X 4 fine multiplication.An anti-SINC FIR filter is used to samples resulting in a compression ratio of 51:1.Thus,by compensate the loss of D/A converter's frequency response taking advantage of sine and cosine symmetries,the size before D/A output.The coefficients of this filter are Canonic of the look-up table ROM is only 1/51 of that of tradi- Signed-Digit(CSD)code,which utilize minimum shift-adder to tional one. complete multiplication operation avoiding many of complicated multiplications.The internal control word registers (such as 2.1.2 Quadrature Ouputs FCW,Phase offset)are wrote or read through a simple For a design where quadrature outputs are desired,a simple microcontroller to reduce the number of 1/O pads of control method would be to store both sine and cosine samples from 0 to signals /2.This would double the size of the ROM look-up table Instead,one could take advantage of one-eighth wave symmetry 2.ARCHITECTURE DESIGN ISSUES of a sine and cosine waveform,since cosine samples from 0 to /4 are the same as sine samples from /4 to n/2.Similarly,sine 2.1 Direct Digital Frequency Synthesizer sample from 0 to n/4 are the same as cosine sample from i/4 to /2.Hence,one need only store sine and cosine samples from 0 This design is based on the optimized architecture of Nicholas to /4.The third MSB of the phase accumulator can be used to and Samueli[2],Zhangwen Tang and Han Min[3].The optimi- select between these samples. zation of direct digital frequency synthesizer (DDFS)involves trading off the finite word lengths and sine computation methods 2.1.3 Modulation Capabilities against the sine-wave spectral purity and maximum clock rate. The modulation capabilities [5]of this chip include frequency Fig.4 shows a block diagram of DDFS in this design,which modulation,phase modulation,quadrature amplitude modulation, employs eighth sine waveform compression algorithms to and frequency mixing.Frequency modulation is performed decrease the volume of the ROM look-up table. directly by modulating the Frequency Control Word.Phase 2.1.1 1/8 Sine Waveform Compression Technique modulation is obtained by adding a phase offset to the phase accumulator output before addressing the ROM look-up table. As we all known,arbitrary functions can be partitioned into Furthermore,this chip accepts only an 8-bit word for phase coarse and fine ROM samples [2],[3].[4].Let A+B+C be total modulation.Finally,quadrature amplitude modulation and number of bits of the phase address,with A being the most frequency mixing are obtained by adding a complex multiplier significant bits,B the next most significant bits,and C the least block to the sine and cosine outputs of the quadrature DDFS as significant bits.Then using this algorithm,the coarse ROM shown in Fig.5.The word length for I and Q rails for amplitude would have 24+B samples,and the fine ROM would have 24+c modulation are 12 bits each.The complex multiplier block is samples.According to the conclusion in [4],A=4,B=4 and C=4 made up of two 12-bit X 12-bit multipliers. is optimal.The output word length of the coarse ROM is 11 bits, I-2In this paper, the word length of the phase accumulator is 32 bits and the maximum clock frequency is 200MHz. Thus the minimum frequency resolution is 0.0466Hz. The switching speed between two frequencies is one clock cycle, 5ns. Fig. 3 is the architecture of the quadrature frequency syn￾thesizer/mixer, which consists of four main modules: direct digital frequency synthesizer, modified Booth multiplier with Wallace adder tree, anti-SINC FIR filter with CSD coefficients and a simple microcontroller. Direct digital frequency synthesizer employs one-eighth sine waveform compression algorithms to achieve high frequency resolution and high bandwidth. 12-bitᱢ12-bit multipliers adopt modified Booth encode and Wal-lace adder tree to improve the speed of multiplication. An anti-SINC FIR filter is used to compensate the loss of D/A converter’s frequency response before D/A output. The coefficients of this filter are Canonic Signed-Digit (CSD) code, which utilize minimum shift-adder to complete multiplication operation avoiding many of complicated multiplications. The internal control word registers (such as FCW, Phase offset) are wrote or read through a simple microcontroller to reduce the number of I/O pads of control signals. 2. ARCHITECTURE DESIGN ISSUES 2.1 Direct Digital Frequency Synthesizer This design is based on the optimized architecture of Nicholas and Samueli[2], Zhangwen Tang and Han Min[3]. The optimi￾zation of direct digital frequency synthesizer (DDFS) involves trading off the finite word lengths and sine computation methods against the sine-wave spectral purity and maximum clock rate. Fig. 4 shows a block diagram of DDFS in this design, which employs eighth sine waveform compression algorithms to decrease the volume of the ROM look-up table. 2.1.1 1/8 Sine Waveform Compression Technique As we all known, arbitrary functions can be partitioned into coarse and fine ROM samples [2], [3], [4]. Let A+B+C be total number of bits of the phase address, with A being the most significant bits, B the next most significant bits, and C the least significant bits. Then using this algorithm, the coarse ROM would have 2A+B samples, and the fine ROM would have 2A+C samples. According to the conclusion in [4], A=4, B=4 and C=4 is optimal. The output word length of the coarse ROM is 11 bits, and that of the fine ROM is 4 bits. Thus, 214h12 sine samples are compressed into 28h11 coarse samples and 28h4 fine samples resulting in a compression ratio of 51:1. Thus, by taking advantage of sine and cosine symmetries, the size of the look-up table ROM is only 1/51 of that of tradi￾tional one. 2.1.2 Quadrature Ouputs For a design where quadrature outputs are desired, a simple method would be to store both sine and cosine samples from 0 to ʌ/2. This would double the size of the ROM look-up table. Instead, one could take advantage of one-eighth wave symmetry of a sine and cosine waveform, since cosine samples from 0 to ʌ/4 are the same as sine samples from ʌ/4 to ʌ/2. Similarly, sine sample from 0 to ʌ/4 are the same as cosine sample from ʌ/4 to ʌ/2. Hence, one need only store sine and cosine samples from 0 to ʌ/4. The third MSB of the phase accumulator can be used to select between these samples. 2.1.3 Modulation Capabilities The modulation capabilities [5] of this chip include frequency modulation, phase modulation, quadrature amplitude modulation, and frequency mixing. Frequency modulation is performed directly by modulating the Frequency Control Word. Phase modulation is obtained by adding a phase offset to the phase accumulator output before addressing the ROM look-up table. Furthermore, this chip accepts only an 8-bit word for phase modulation. Finally, quadrature amplitude modulation and frequency mixing are obtained by adding a complex multiplier block to the sine and cosine outputs of the quadrature DDFS as shown in Fig. 5. The word length for I and Q rails for amplitude modulation are 12 bits each. The complex multiplier block is made up of two 12-bith12-bit multipliers. MCU DDFS CORE X sin(x) 8 12 12 I Q D WR_clk WR_en FQ_UD 32 FCW 8 Phase cosZn sinZn 12 12 23 23 12 12 COM clk Fig. 3. Architecture of Quadrature Frequency Synthesizer/Mixer 2:2 MUX 2:2 MUX 2:2 MUX Coarse ROMA Coarse ROMB Fine ROMA Fine ROMB + + 2:2 MUX 2ND MSB 1's compl 1's compl MSB 12 12 sin cos MSB 2ND MSB 12 12 11 11 4 4 11 11 12 12 8 8 8 8 2ND MSB 3RD MSB Q D clk D Flip-Flop FCW ADDER Phase Registers clk carry in Modification 32 14 Fig. 4. Optimized Architecture of DDFS Phase ACCU. (32 bit) ROM LUT Phase Offset Phase Modulation FCW Frequency Modulation 32 14 8 32 12 12 SIN COS 12 12 I Q COM 23 23 Fig. 5. Modulation Capabilities I-2