Typical EDA Tools for Altera FPGA Design Timing Analysis(Quartus Il) -Verify Performance Specifications Were Met May Require Design Edits QUARTUS Gate Level Simulation(Quartus ll or ModelSim) Timing Simulation -Verify Design Will Work in Target Technology May Require Design Edits QUARTUS PC Board Simulation Test (Quartus Il) Simulate Board Design Program Test Device on Board QUARTUS In-System Debugging Tool: Signal Probe,Signal Tap 2021/1/13 ASIC Design,by Yan Bo 10ASIC Design, by Yan Bo Timing Analysis (Quartus II) - Verify Performance Specifications Were Met - May Require Design Edits Gate Level Simulation (Quartus II or ModelSim) - Timing Simulation - Verify Design Will Work in Target Technology - May Require Design Edits PC Board Simulation & Test (Quartus II) - Simulate Board Design - Program & Test Device on Board - In-System Debugging Tool: Signal Probe, Signal Tap Typical EDA Tools for Altera FPGA Design 2021/1/13 10