library ieee; use ieeestd_logic_1164.all use ieee std_logic_unsigned. all; entity scan_led is port(clk:in std_logic; segout std_logic_vector(7 downto O); scan: out std _logic_vector(7 downto O)); d scan led architecture one of scan led is signal cnt: integer range0to7;-数码管地址指针 signal data integer range0to15;--7段译码指针 egin rocess(clky) 用于扫描数码管地址的计数器 begin if clk' event and clk=‘1’then cnt<=cnt+1; end if: end process;library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity scan_led is port(clk:in std_logic; seg:out std_logic_vector(7 downto 0); scan:out std_logic_vector(7 downto 0)); end scan_led; architecture one of scan_led is signal cnt: integer range 0 to 7; --数码管地址指针 signal data:integer range 0 to 15; --7段译码指针 begin process(clk) --用于扫描数码管地址的计数器 begin if clk’event and clk=‘1’ then cnt<=cnt+1; end if; end process;