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黑龙江大学物理科学与技术学院:《EDA教程——EDA技术及应用》第十章 数字系统设计范例(蔡喜平)

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1.设计要求 控制8个LED进行花式显示,设计4中显示模式: S0:从左到右逐个点亮LED; S1:从右到左逐个点亮LED;
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第十章数孤统设计部例 10.1跑马灯设计 1.设计要求 控制8个LED进行花式显示,设计4中显示模式: ●S0:从左到右逐个点亮IFD; ●s1:从右到左逐个点亮LED ●S2从两边到中间逐个点亮LED ●S3:从中间到两边逐个点亮LED 4种模式循环切换,复位键(rst控制系统的运行和停止。 led clkx-时钟 clk rst一复位信号输入端 rst q[7…0 q-数据输出端 led的电路符号

第十章 数字系统设计范例 10.1 跑马灯设计 1.设计要求 控制8个LED进行花式显示,设计4中显示模式: ⚫S0:从左到右逐个点亮LED; ⚫S1:从右到左逐个点亮LED; ⚫S2:从两边到中间逐个点亮LED; ⚫S3:从中间到两边逐个点亮LED; 4种模式循环切换,复位键(rst)控制系统的运行和停止。 led的电路符号 clk q[7…0] clk –时钟 q – 数据输出端 led rst rst – 复位信号输入端

library ieee; use ieeestd_logic_1164.all use ieee std_logic_unsigned. all; entity led is port(elk:in std_ _ logic: rstin std _ logic; g: out std logic__vector(7 downto O)); dled architecture one ofled is type states is(0,s1,2,3;-定义四种模式 signal presentstates signal q1: std_logic_vector(7 downto O) signal countstd _ logic__vector(3 downto O) egn process(clk b egin ifrst=1 then 系统复位 present<=s0; q1 0000000; elsif clk event and clk=1 then

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity led is port(clk:in std_logic; rst:in std_logic; q:out std_logic_vector(7 downto 0)); end led; architecture one of led is type states is (s0,s1,s2,s3); --定义四种模式 signal present:states; signal q1: std_logic_vector(7 downto 0); signal count:std_logic_vector(3 downto 0); begin process(clk,rst) begin if rst=‘1’ then --系统复位 present<=s0; q1<=“00000000”; elsif clk’event and clk=‘1’ then

case present 1s when s0=>ifq1=“00000then-S0模式,从左到右逐个点亮工ED 1 if count=“0111”then-!1模式,从右到左逐个点亮LED count<=“0000 q1<=“10000 resent<=s else q1<=q1(6 downto O)&eq1(); count<=count+1; resent<=s1 end if:

case present is when s0 => if q1=“00000000” then --S0模式,从左到右逐个点亮LED q1 if count=“0111” then --S1模式,从右到左逐个点亮LED count<=“0000”; q1<=“10000001”; present<=s2; else q1<=q1(6 downto 0)&q1(7); count<=count+1; present<=s1; end if;

when s2=> if count=“0111then-S2模式,从两边到中间逐个点亮LED count if count=“0111′then-S3模式,从中间到两边逐个点亮LED count<=“000 1<=“1000000 present<=sO else q1(7 downto 4 <=q1(6 downto 4)&xq1(7 end if Present<=s t+ 9Z q1(3 downto O)<= (O)&eq1(3 downto 1); end case, dife end 9=g end one

when s2 => if count=“0111” then --S2模式,从两边到中间逐个点亮LED count if count=“0111” then --S3模式,从中间到两边逐个点亮LED count<=“0000”; q1<=“10000000”; present<=s0; else q1(7 downto 4)<=q1(6 downto 4)&q1(7); q1(3 downto 0)<=q1(0)&q1(3 downto 1); count<=count+1; present<=s3; end if; end case; end if; end process; q<=q1; end one;

0. 19.9ns L厂L厂 B OOC 000000×10000000100000010000×0010000000X000010x00000 00000001 X000000 rst presen present, so resent. sI

10.28位数码扫描显示电路设计 要求:在8个数码管上显示数据“124579DF” 原理:K1Kg选通信号; K K5 K 8位数码扫描显示电路 Scan led clk-时钟 clk scan-地址选择控制信号输入端 seg-段显示控制信号输出端 scan/…… 8位数码管扫描显示电路的电路符号

10.2 8位数码扫描显示电路设计 a g K1 a g K2 a g K3 a g K4 a g K5 a g K6 a g K7 a g K8 要求:在8个数码管上显示数据“124579DF” 原理:K1 -K8 :选通信号; 8位数码扫描显示电路 8位数码管扫描显示电路的电路符号 clk scan[7…0] clk –时钟 seg – 段显示控制信号输出端 Scan_led scan – 地址选择控制信号输入端 seg[7…0]

library ieee; use ieeestd_logic_1164.all use ieee std_logic_unsigned. all; entity scan_led is port(clk:in std_logic; segout std_logic_vector(7 downto O); scan: out std _logic_vector(7 downto O)); d scan led architecture one of scan led is signal cnt: integer range0to7;-数码管地址指针 signal data integer range0to15;--7段译码指针 egin rocess(clky) 用于扫描数码管地址的计数器 begin if clk' event and clk=‘1’then cnt<=cnt+1; end if: end process;

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity scan_led is port(clk:in std_logic; seg:out std_logic_vector(7 downto 0); scan:out std_logic_vector(7 downto 0)); end scan_led; architecture one of scan_led is signal cnt: integer range 0 to 7; --数码管地址指针 signal data:integer range 0 to 15; --7段译码指针 begin process(clk) --用于扫描数码管地址的计数器 begin if clk’event and clk=‘1’ then cnt<=cnt+1; end if; end process;

process(cnt) 数码管地址扫描 begin case catis when0=>scanscanscanscanscanscanscanscan nule end case; end process

process(cnt) --数码管地址扫描 begin case cnt is when 0 => scan scan scan scan scan scan scan scan null; end case; end process;

process(data 7段译码 egin case data is when0=>segsegsegsegsegsegsegsegsegsegsegsegsegsegseg<=110001110; when others = null end case end process; end one:

process(data) -- 7段译码 begin case data is when 0 => seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg null; end case; end process; end one;

20.0 20.0ns E scan B 000c o000d00000010 00000100 00001000 X 00010000 X 00100000 01000000 10000000 X 00000001 X 00000010 00000100X00001000 od 国s8Bo!kgx1010ox0n000x1010n0X100o1o10xon100x10011x010000101001010X1010110X AC KTO L [5 [6

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