FPGA Design Method Design flow & tools Deign Model of Verilog HDL Design style of Verilog HDL Design Examples • RTL level design • Components of Datapath • Components of Controller

Verilog for Verification • Testbench anatomy • Behavioral modeling for Testbench • Some examples Timing specification • Delay model • Timing verification • Pipeline technology Design For Test (DFT) Test vs. Verification Build In Self Test (BIST) Scan and Boundary Scan

Digital Signal Processing • Signal & System • DSP system • Description for DSP FIR Filter Design & Implement • Digital Filter • Specification Design • Hardware Implementation Some Examples • Digital Down Converter • Central Processing Unit

3.1 极大似然 3.2 隐变量 3.3 EM算法 3.4 混合高斯模型中的EM思想 3.5 论文举例

• 2.1 Introduction • 2.2 Polynomial Curve Fitting: A Toy • 2.3 Over-fitting • 2.4 Cross-Validation • 2.5 Regularization • 2.6 Linear Basis Function Models • 2.7 Least Squares Revisited • 2.8 Bayesian Linear Regression

3.1 Sparsity: Applications and Development 3.2 Sparsity Rendering Algorithms 3.3 EM 3.4 Variational Bayes 3.5 Sparse Signal Recovery: Performance PK 3.6 Other Applications for Bayes methods

1.1 Wireless Channels 1.2 Single Antenna Channels 1.3 Multiple Antenna Channels 1.4 Introduction of Random Matrix

本章介绍利用独立电流或独立电压作变量来建立电路方程的分析方法，可以减少联立求解方程的数目，适合于求解稍微复杂一点的线性电阻电路，是“笔”算求解线性电阻电路最常用的分析方法

• 输入电阻 • 输出电阻 • 电压放大模型 • 电流放大模型 1.2.1 模拟信号的放大 1.2.2 放大电路模型 1.2.3 放大电路的主要性能指标 • 增益 • 互阻放大模型 • 互导放大模型 • 隔离放大电路模型 • 频率响应及带宽 • 非线性失真

2.1 Discrete-Time Signals: Time-Domain Representation Signals represented as sequences of numbers, called samples Sample value of a typical signal or sequence denoted as x[n] with n being an integer in the range-oo≤n≤∞ x[n] defined only for integer values of n and undefined for noninteger values of n Discrete-time signal represented by {x[n]}