高级计算机体系结构设计及其在数据中心和云计算的应用Lecture 3Main Memory and DRAM Technology
高级计算机体系结构设计及其在数据中心和云计算的应 用 Lecture 3 Main Memory and DRAM Technology
高级计算机体系结构设计及其在数据中心和云计算的应用SRAM VS. DRAMSRAM = StaticRAM- As long as power is present, data is retainedDRAM=DynamicRAM- If you don't do anything, you lose the dataSRAM: 6T per bit- built with normal high-speed CMos technologyDRAM: 1T per bit (+1 capacitor)- built with special DRAM process optimized for density
高级计算机体系结构设计及其在数据中心和云计算的应 用 SRAM vs. DRAM • SRAM = Static RAM – As long as power is present, data is retained • DRAM = Dynamic RAM – If you don’t do anything, you lose the data • SRAM: 6T per bit – built with normal high-speed CMOS technology • DRAM: 1T per bit (+1 capacitor) – built with special DRAM process optimized for density
高级计算机体系结构设计及其在数据中心和云计算的应用Hardware StructuresSRAMDRAMwordlinewordlinebbb
高级计算机体系结构设计及其在数据中心和云计算的应 用 Hardware Structures b b SRAM wordline b DRAM wordline
高级计算机体系结构设计及其在数据中心和云计算的应用Implementing the Capacitor (1/2)You can use a “dead" transistor gate:But this wastes area becausewenowhavetwotransistorsCapacitorM,wordlineAndthe“dummy"transistormayneedDiffusedto bebiggertohold enoughchargebit linePolysiliconPolysiliconplategate
高级计算机体系结构设计及其在数据中心和云计算的应 用 Implementing the Capacitor (1/2) • You can use a “dead” transistor gate: But this wastes area because we now have two transistors And the “dummy” transistor may need to be bigger to hold enough charge
高级计算机体系结构设计及其在数据中心和云计算的应用Implementing the Capacitor (2/2)There are other advanced structuresCell Plate Si"Trench Cell"CapInsulatorReflling PolyStorageNodePolySi SubstrateField Oxide
高级计算机体系结构设计及其在数据中心和云计算的应 用 Implementing the Capacitor (2/2) • There are other advanced structures “Trench Cell” Cell Plate Si Cap Insulator Storage Node Poly Field Oxide Refilling Poly Si Substrate
高级计算机体系结构设计及其在数据中心和云计算的应用DRAM Chip Organization (1/2)THdecoderRow2H2HAddressHHHH-宁HHTX主TTSenseAmpsOColumnmultiplexorAddressDRAMismuchdenserthanSRAM
高级计算机体系结构设计及其在数据中心和云计算的应 用 DRAM Chip Organization (1/2) Row Address Column Address Row Buffer multiplexor DRAM is much denser than SRAM decoder Sense Amps
高级计算机体系结构设计及其在数据中心和云计算的应用DRAM Chip Organization (2/2)Low-Level organization is very similar to SRAM. Cells are only single-ended- Reads destructive: contents are erased by readingRowbufferholds read data-DatainrowbufferiscalledaDRAMrow· Often called“page"- not necessarily same as Os page-Read gets entirerowinto the buffer-Blockreadsalwaysperformedoutof therowbuffer.Readinga wholerow,but accessing oneblock· Similar to reading a cache line, but accessing one word
高级计算机体系结构设计及其在数据中心和云计算的应 用 DRAM Chip Organization (2/2) • Low-Level organization is very similar to SRAM • Cells are only single-ended – Reads destructive: contents are erased by reading • Row buffer holds read data – Data in row buffer is called a DRAM row • Often called “page” - not necessarily same as OS page – Read gets entire row into the buffer – Block reads always performed out of the row buffer • Reading a whole row, but accessing one block • Similar to reading a cache line, but accessing one word
高级计算机体系结构设计及其在数据中心和云计算的应用Destructive ReadsenseampoutputVadddbitlinevoltage//NASenseAmpEnabledSenseAmpEnabledWordlineEnabledWordlineEnabled1dcapacitorvoltageAfterread ofOor1,cell contentscloseto /2
高级计算机体系结构设计及其在数据中心和云计算的应 用 Destructive Read 0 bitline voltage capacitor voltage Vdd Wordline Enabled Sense Amp Enabled sense amp output Vdd 1 After read of 0 or 1, cell contents close to ½ Vdd Wordline Enabled Vdd Sense Amp Enabled
高级计算机体系结构设计及其在数据中心和云计算的应用DRAMRead: After a read, the contents of the DRAM cell are gone-But still"safe"inthe rowbufferWrite bits back before doing another readReading into buffer is slow, but reading buffer is fast- Try reading multiple lines from buffer (row-buffer hit)DRAMcellsSenseAmpsRow BufferProcessiscalled opening orclosinga row
高级计算机体系结构设计及其在数据中心和云计算的应 用 DRAM Read • After a read, the contents of the DRAM cell are gone – But still “safe” in the row buffer • Write bits back before doing another read • Reading into buffer is slow, but reading buffer is fast – Try reading multiple lines from buffer (row-buffer hit) Sense Amps DRAM cells Row Buffer Process is called opening or closing a row
高级计算机体系结构设计及其在数据中心和云计算的应用DRAM Refresh (1/2).Gradually,DRAM cell loses contents-Even if it's notaccessed- This is why it's called “dynamic"Gate Leakage DRAM must be regularly read and re-written- What to do if no read/write to row for long time?capacitorvoltageLong TimeMustperiodicallyrefreshall contents
高级计算机体系结构设计及其在数据中心和云计算的应 用 DRAM Refresh (1/2) • Gradually, DRAM cell loses contents – Even if it’s not accessed – This is why it’s called “dynamic” • DRAM must be regularly read and re-written – What to do if no read/write to row for long time? 1 Gate Leakage 0 Must periodically refresh all contents capacitor voltage Vdd Long Time