复旦大学：《材料失效分析 Materials Failure Analysis》课程教学资源（教学案例）53. Failure analysis on blind vias of PCB for novel mobile phones

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J Fail. Anal. and Preven. (2008)8: 524-532 DOI0.10071168001741 CASE HISTORY-PEER-REVIEWED Failure Analysis on Blind vias of PCB for Novel Mobile Phones Li-NaJi· Zhen-Guo Yang·Jian- Sheng liu Submitted: 15 February 2008/in revised form: 17 August 2008/Published online: 17 September 2008 C ASM International 2008 Abstract Failure of blind via is one of the main causes of introduction an open circuit in printed circuit boards(PCBs). By using macroscopic and microscopic testing methods and char- With the expansion of high-density interconnection(HDD acterization techniques, the failure analysis of the vias on in electronic packaging technology, blind via is a newly PCB for novel mobile phones has been systematically developed type of microvia, providing electrical intercon carried out. Metallographic inspection shows obvious nection among different laminates of a printed circuit board racking along the interface of different copper layers. (PCB). Blind vias comprise electroless copper on top of Micrograph observation and chemical analysis on the grain buried interconnects formed from various kinds of copper boundary have definitely identified that inappropriate foil and underneath subsequent coatings of electroplated location of the vias concerned with circuit design and copper. Blind vias can be constructed by laser ablating the residue sulfur related to incomplete desmear process pre- holes in the top layer of the board material. Holes formed dominantly account for cracking of blind and the are then cleaned and a layer of electroless copper deposited occurrence of the cracking is caused by the formation of a in the hole, followed by coatings of electroplated copper on brittle Curs layer. Moreover, the influence of warpage top of that layer [1]. Therefore, inappropriate circuit and the reliability of the via was noted. Based on these defaults, geometry design, improper manufacturing process, and improvement countermeasures and suggestions poor plating quality can directly affect yield and electrical addressed in the paper and are of significant value for reliability of PCB. An open circuit is one of the frequent reference to the safe reliability and structural integrity of faults that occur during manufacturing [2] PCB products during manufacturing and services Blind vias play a crucial role in HDI packaging tech- nology because of their desirable electrical performance and Keywords Blind via. Cracking Sulfur embrittlement. low reflection. However, it is critical to evaluate the reli- PCB· Failure analysis ability of these structures. The technologies for manufacturing blind vias have been addressed 3, 4. The thermomechanical reliability of them is usually evaluated theoretically by experimental tests such as FEM simulation and impact tests etc [5-8]. However, comprehensive anal- LN.J·ZG.Ya yses on failure of blind vias after actual services have rarely Department of Materials Science, Fudan University been reported. Marks [9]introduced several practical failure Shanghai 200433 China cases of fip-chip packaging, but skipped the research on e-mail:zgyang@fudan.edu.cn blind vias. Also, the chemical mechanism for the cracking L-N. Ji generation in the vias has not been well studied. e-mail:lisa0119@126.com Based on our former study on failure ball grid array J-S. Liu (BGA) solder joints [10], further analysis on blind vias of China Circuit Technology (Shantou)Corporation(CCTC). the two types of PCB was carried out. Since Guangdong 515041 chir inspection is the first and important step in 2 Springer

CASE HISTORY—PEER-REVIEWED Failure Analysis on Blind Vias of PCB for Novel Mobile Phones Li-Na Ji Æ Zhen-Guo Yang Æ Jian-Sheng Liu Submitted: 15 February 2008 / in revised form: 17 August 2008 / Published online: 17 September 2008 ASM International 2008 Abstract Failure of blind via is one of the main causes of an open circuit in printed circuit boards (PCBs). By using macroscopic and microscopic testing methods and characterization techniques, the failure analysis of the vias on PCB for novel mobile phones has been systematically carried out. Metallographic inspection shows obvious cracking along the interface of different copper layers. Micrograph observation and chemical analysis on the grain boundary have definitely identified that inappropriate location of the vias concerned with circuit design and residue sulfur related to incomplete desmear process predominantly account for cracking of blind vias, and the occurrence of the cracking is caused by the formation of a brittle CuxS layer. Moreover, the influence of warpage on the reliability of the via was noted. Based on these defaults, improvement countermeasures and suggestions are addressed in the paper and are of significant value for reference to the safe reliability and structural integrity of PCB products during manufacturing and services. Keywords Blind via Cracking Sulfur embrittlement PCB Failure analysis Introduction With the expansion of high-density interconnection (HDI) in electronic packaging technology, blind via is a newly developed type of microvia, providing electrical interconnection among different laminates of a printed circuit board (PCB). Blind vias comprise electroless copper on top of buried interconnects formed from various kinds of copper foil and underneath subsequent coatings of electroplated copper. Blind vias can be constructed by laser ablating the holes in the top layer of the board material. Holes formed are then cleaned and a layer of electroless copper deposited in the hole, followed by coatings of electroplated copper on top of that layer [1]. Therefore, inappropriate circuit and geometry design, improper manufacturing process, and poor plating quality can directly affect yield and electrical reliability of PCB. An open circuit is one of the frequent faults that occur during manufacturing [2]. Blind vias play a crucial role in HDI packaging technology because of their desirable electrical performance and low reflection. However, it is critical to evaluate the reliability of these structures. The technologies for manufacturing blind vias have been addressed [3, 4]. The thermomechanical reliability of them is usually evaluated theoretically by experimental tests such as FEM simulation and impact tests etc. [5–8]. However, comprehensive analyses on failure of blind vias after actual services have rarely been reported. Marks [9] introduced several practical failure cases of flip-chip packaging, but skipped the research on blind vias. Also, the chemical mechanism for the cracking generation in the vias has not been well studied. Based on our former study on failure ball grid array (BGA) solder joints [10], further analysis on blind vias of the two types of PCB was carried out. Since visual inspection is the first and important step in failure L.-N. Ji Z.-G. Yang (&) Department of Materials Science, Fudan University, Shanghai 200433, China e-mail: zgyang@fudan.edu.cn L.-N. Ji e-mail: lisa0119@126.com J.-S. Liu China Circuit Technology (Shantou) Corporation (CCTC), Guangdong 515041, China 123 J Fail. Anal. and Preven. (2008) 8:524–532 DOI 10.1007/s11668-008-9174-1

J Fail. Anal. and Preven.(2008)8: 524-532 525 investigation [11 a series of modern analytical instruments and methods such as stereomicroscope, optical microscop (OM), and digital microscope(3D)were used to observe the failure. The scanning electron microscope(SEM), energy dispersive spectroscopy(EDS), and focus ion beam(FIB were adopted to reveal the cracking morphologies and chemical compositions of the vias. Characterization tech niques such as Fourier transform infrared spectroscopy (FT-IR), thermogravimetric analyses(TGA), and scanning acoustic microscopy (SAM) were also used to inspect the bare board. The cracking mechanism and the causes of the ⊙⊙ failure were definitely revealed. Preventive countermea sures and suggestions are given in this paper Brief Introduction of the Failed PcBs (a) Figure i shows the circuit configuration of both sides omponents on two types of PCBs, respectively. dimension of92×37×1. I mm for type I 81 38 x 0.98 mm for type 2. Open-circuit faults have been detected mainly around BGA solder joints and solder bars of several components and chips by automatic optical inspection(AOD). The faults induce failure of the whole board. During macroscopic inspection, circuit configura- tions of components on type 1 PCB are not distorted, but obvious warpage has been found in type 2 PCB. Modern analytic instruments and characterization methods have ⊙.⊙· been adopted in order to find the primary causes. Characterization and microstructural observation (b) The results of FT-IR(Fig. 2)show that the two types of PCb Fig. 1 Circuit configuration with components on PCBs (a)fror have an FR-4 flame-resistant substrate and that the raw back face of Type I PCB. (b) Front and back face of Type 2 materials are all bromized epoxy resin. TGA curves in Fig. 3 indicate that the materials reach their thermal decomposi- reflow soldering or service. Moreover, the mismatch of tion temperature(Ta) at about 323C. The Ta of bromized coefficient of thermal expansion( CTE) between the plating epoxy resin is generally above 300C, and the soldering layer and copper foil will enhance the thermal stress, peak temperature in surface mounting technology(SMT)of finally resulting in the fracture from one side of the via PCB is below 270C. Therefore, the raw materials can The location of the blind via in Fig. 5 indicates that the via endure the instantaneous high temperature and the failure and the BGa solder pad are too close to each other, just should have no relationship to the soldering processes. like the case shown in Fig. 4. An obvious microvoid in the Microscopic study was carried out at low magnification copper foil, in which there appeared to be some debris, and using stereomicroscope and at higher magnification using an apparent crack in the bottom of the via, are displayed in PCBs From Fig 4(c)and(d), distinct cracking can be seen observed by SEM, and chemical compositions along the in the center of the via. Consequently, a strong thermal and the microstructure near cracking is presented in Fig. 8 stress will occur around part of the via, leading to an SAM with a sensor of 100 mhz was used to detect asymmetric thermal deformation under conditions of delamination of the PCB before and after the thermal 2 Springer

investigation [11], a series of modern analytical instruments and methods such as stereomicroscope, optical microscope (OM), and digital microscope (3D) were used to observe the failure. The scanning electron microscope (SEM), energy dispersive spectroscopy (EDS), and focus ion beam (FIB) were adopted to reveal the cracking morphologies and chemical compositions of the vias. Characterization techniques such as Fourier transform infrared spectroscopy (FT-IR), thermogravimetric analyses (TGA), and scanning acoustic microscopy (SAM) were also used to inspect the bare board. The cracking mechanism and the causes of the failure were definitely revealed. Preventive countermeasures and suggestions are given in this paper. Brief Introduction of the Failed PCBs Figure 1 shows the circuit configuration of both sides with components on two types of PCBs, respectively, with dimension of 92 9 37 9 1.1 mm for type 1 and 81 9 38 9 0.98 mm for type 2. Open-circuit faults have been detected mainly around BGA solder joints and solder bars of several components and chips by automatic optical inspection (AOI). The faults induce failure of the whole board. During macroscopic inspection, circuit configurations of components on type 1 PCB are not distorted, but obvious warpage has been found in type 2 PCB. Modern analytic instruments and characterization methods have been adopted in order to find the primary causes. Characterization and Microstructural Observation The results of FT-IR (Fig. 2) show that the two types of PCB have an FR-4 flame-resistant substrate and that the raw materials are all bromized epoxy resin. TGA curves in Fig. 3 indicate that the materials reach their thermal decomposition temperature (Td) at about 323 C. The Td of bromized epoxy resin is generally above 300 C, and the soldering peak temperature in surface mounting technology (SMT) of PCB is below 270 C. Therefore, the raw materials can endure the instantaneous high temperature and the failure should have no relationship to the soldering processes. Microscopic study was carried out at low magnification using stereomicroscope and at higher magnification using OM and 3D. Figures 4 and 5, respectively, present the morphologies of the failure blind vias on both types of PCBs. From Fig. 4(c) and (d), distinct cracking can be seen between the copper plating layer and the pad of the blind via. As illustrated in Fig. 4(b), the pad is not located right in the center of the via. Consequently, a strong thermal stress will occur around part of the via, leading to an asymmetric thermal deformation under conditions of reflow soldering or service. Moreover, the mismatch of coefficient of thermal expansion (CTE) between the plating layer and copper foil will enhance the thermal stress, finally resulting in the fracture from one side of the via. The location of the blind via in Fig. 5 indicates that the via and the BGA solder pad are too close to each other, just like the case shown in Fig. 4. An obvious microvoid in the copper foil, in which there appeared to be some debris, and an apparent crack in the bottom of the via, are displayed in Fig. 5(c) and (d). Cracking morphologies of the blind vias were further observed by SEM, and chemical compositions along the fracture line were analyzed by EDS in Figs. 6 and 7. A FIB was used to etch part of the surface of the deposited copper, and the microstructure near cracking is presented in Fig. 8. SAM with a sensor of 100 MHz was used to detect delamination of the PCB before and after the thermal Fig. 1 Circuit configuration with components on PCBs. (a) Front and back face of Type 1 PCB. (b) Front and back face of Type 2 PCB J Fail. Anal. and Preven. (2008) 8:524–532 525 123

main cause of failure. The analytical results show that it is the defect of the blind vias that leads to the open circuits. A big open cracking from one side of the blind via with a result of a separation completely between the pad and the copper-plating layer is shown in Fig. 6. An obvious cracking from the bottom of the other blind via that partly separated the via and the copper foil is presented in Fig. 7. We can also notice from the location of these two blind vias that the design position between pads and blind vias is somewhat improper. They are not kept in the same Z-direction, and the distance between them is too small. Usually, the region close packed with deep color dots shows a comparatively faster rate of heating. Therefore, temperature around the pads covered with solder of dark color rises faster than pad areas without solder during the heating for reflow soldering; while temperature in the areas with just the pads drops faster than in those overlaid with solder in the cooling segment of reflow soldering. The mismatch CTE of these two areas results in a strong thermal stress and an asymmetric deformation in the blind vias linked closely to the pad uncovered with solder. Accordingly, the improper circuit design regarding the location of blind vias and pads is the leading cause of vias cracking. In addition, the EDS results (Fig. 6c and 7c) demonstrate that a certain amount of sulfur which usually leads to embrittlement concentrates at the interface. Higher magnifications of the cracking and many microcracks can be seen in Fig. 7(d)–(g). These microcracks are generated along the deposited copper grains. Microstructure of the grains near cracking has also been obtained by FIB, with a sound characteristic of intercrystalline fracture. It can be Fig.4 (a) Location of the failure blind via (type 1). (b) Appearance of the via. 4.59 (c) and (d) Cracking morphologies by 3D and OM. 409 and 609 Fig. 3 TGA curve of bare board. (a) Type 1. (b) Type 2 J Fail. Anal. and Preven. (2008) 8:524–532 527 123

J Fail. Anal and Preven.(2008)8: 524-532 m Fig 8 FIB microstructure(a) Etching section. (b)and(c) Morphologies of the cracking Table 1 Conditions of thermal cycle testing on the bare board segregated to the surface along the different layers of the Range of cycle temperature, C 40125 vias probably nucleated as a set of three-dimensional islands of Cu s, which would be expected to grow until 13(up)+ 20(remaining) Cool-down cycle, (down)+20 (remaining) or grain-boundary intersections with the surface [15].This Times for thermal cycle is highly undesirable, and there are several structura transformations of Curs in the temperature interval of eDs is far above the standard. as is shown in the former interest. These transformations favor the fatal crack part. Thus, it can be assumed that this embrittlement nucleation and propagation at grain boundaries under the fracture is largely affected by segregation of S at grain thermal stress generated during reflow soldering. Conse quently, the conclusion can be reached that the residue of s Although the structure formed by the segregated S at impurity along copper grain boundary has a significant grain boundaries is still unknown, the formation of Cu,s infiuence on the reliability of the blind vias, which is the ompounds can be expected, especially Cu2S. Similar predominant cause of the failure. The residue S primarily evidence was also found by Boulliard and Sotto [13] that results from the desmear process and the cleaning of the the structure of segregated sulfur on the face of Cu(100) blind vias. single crystals was 8 S atoms on 17 Cu atoms, with the s Moreover, through macroscopic observation, apparent atoms arranged in a p(2 x 2)lattice. Note that this cov- warpage can be noticed in type 2 PCB with a discrepancy erage approximates the stoichiometry of Cu2S phase of about 1 mm between the right and left sides of the which is highly stable [14]. It was also reported that the board. As mentioned previously, the type 2 PCB is only phase transition from the "high chalcocite"hexagonal 0.98 mm thick, the thickness of which is at least 10% phase to the complex"low chalcocite"phase occurs at thinner than that of type I PCB. It is both the improper 1035C for x= 2.000, but drops to 90oC for the slightly reduction of the thickness and asymmetric configuration of more sulfur-rich compound with x =1990 components on the board that lead to the excessive war- Hence, the mechanism of the cracking generation in the page and deformation of the board, which will produce a blind vias occurs through the following steps. The sulfur big tensile force or a bending stress around pads linked 2 Springer

EDS is far above the standard, as is shown in the former part. Thus, it can be assumed that this embrittlement fracture is largely affected by segregation of S at grain boundary. Although the structure formed by the segregated S at grain boundaries is still unknown, the formation of CuxS compounds can be expected, especially Cu2S. Similar evidence was also found by Boulliard and Sotto [13] that the structure of segregated sulfur on the face of Cu (100) single crystals was 8 S atoms on 17 Cu atoms, with the S atoms arranged in a p(2 9 2) lattice. Note that this coverage approximates the stoichiometry of Cu2S phase, which is highly stable [14]. It was also reported that the phase transition from the ‘‘high chalcocite’’ hexagonal phase to the complex ‘‘low chalcocite’’ phase occurs at 103.5 C for x = 2.000, but drops to 90 C for the slightly more sulfur-rich compound with x = 1.990. Hence, the mechanism of the cracking generation in the blind vias occurs through the following steps. The sulfur segregated to the surface along the different layers of the vias probably nucleated as a set of three-dimensional islands of CuxS, which would be expected to grow until they coalesced. The nucleation sites may be at dislocation or grain-boundary intersections with the surface [15]. This is highly undesirable, and there are several structural transformations of CuxS in the temperature interval of interest. These transformations favor the fatal crack nucleation and propagation at grain boundaries under the thermal stress generated during reflow soldering. Consequently, the conclusion can be reached that the residue of S impurity along copper grain boundary has a significant influence on the reliability of the blind vias, which is the predominant cause of the failure. The residue S primarily results from the desmear process and the cleaning of the blind vias. Moreover, through macroscopic observation, apparent warpage can be noticed in type 2 PCB with a discrepancy of about 1 mm between the right and left sides of the board. As mentioned previously, the type 2 PCB is only 0.98 mm thick, the thickness of which is at least 10% thinner than that of type 1 PCB. It is both the improper reduction of the thickness and asymmetric configuration of components on the board that lead to the excessive warpage and deformation of the board, which will produce a big tensile force or a bending stress around pads linked Fig. 8 FIB microstructure. (a) Etching section. (b) and (c) Morphologies of the cracking Table 1 Conditions of thermal cycle testing on the bare board Range of cycle temperature, C -40–125 Heat-up cycle, min 13 (up) ? 20 (remaining) Cool-down cycle, min 17 (down) ? 20 (remaining) Times for thermal cycle 200 530 J Fail. Anal. and Preven. (2008) 8:524–532 123

J Fail. Anal. and Preven.(2008)8: 524-532 Conclusions The comprehensive analysis on the two types of PCBs by both macroscopic and microscopic methods shows that cracking of the blind vias causes open-circuit faults the PCBs. the raw materials of the boards are acceptable, and there is also no noticeable delamination around the failure sections Improper locations of pads and blind vias are based or improper circuit design, and lead to high stresses and asymmetry deformations that generate cracking some weak joints once heated. Therefore, the design default is a primary cause for cracking of the blind vias The residue S appearing in the wall interface of the blind vias has a fatal effect on the structural integrity and deposition quality of the copper plating with a formation f Curs in the interface of copper grains. The structure of Curs can change with different temperatures, induc- ing an embrittlement intercrystalline fracture during SMT. Accordingly, the incomplete desmear is the predominant factor for failure of the vias An inappropriate reduction in thickness of type 2 PCB and together with the asymmetric configuration of compo- Gate Pos: 16ns width 88 n nents lead to excessive warpage and deformation of the ig tensile force or a bendi stress around pads linked with blind vias. However, under some conditions, cracking will occur in those weak connections of the vias. So. the unsuitable dimension design of the PCB is another potential risk of failure. 680069007000710072007007400750m Suggestions alax It is advised that the design of relative locations among Gate Pos: 9712ns width 62 ns 61 pads and components should be optimized through simulation (FEM) and bench test inspection on the wall of the blind vias should be emphasized before plating to provide a clean wall surface. (d) The best thickness of the board should be simulated 4009500960097009800 hrough FEM and essential property experiments to Fig 9 SAM inspection of the bare board before and after therma ensure adequate stiffness of the substrate cycle test. (a)Before testing.(b) After testing.(e) Spectra before sting.(d) Spectra after testin Acknowledgment The financial support by both the Shanghai Leading Academic Discipline Project(Project Number: B113) and China Circuit Technology(Shantou) Corporation (CCTC)(Grant with blind vias, leading to a cracking in some weak con- SGH2021073)is acknowledged. nections of different layers in the In summary, both the improper location design of pads and blind vias and the incomplete desmear process before References copper plating constitute the main causes of the cracking The inappropriate dimension design of type 2 PCB I. Richard, S, Jamal, H, Prado, E: High-density PWB microvia liability for space application. Aerosp. Conf. 3-10 March another potential risk of failure 2007,正EE,Pp.l-8(2007 2 Springer

with blind vias, leading to a cracking in some weak connections of different layers in the vias. In summary, both the improper location design of pads and blind vias and the incomplete desmear process before copper plating constitute the main causes of the cracking. The inappropriate dimension design of type 2 PCB is another potential risk of failure. Conclusions • The comprehensive analysis on the two types of PCBs by both macroscopic and microscopic methods shows that cracking of the blind vias causes open-circuit faults in the PCBs. The raw materials of the boards are acceptable, and there is also no noticeable delamination around the failure sections. • Improper locations of pads and blind vias are based on improper circuit design, and lead to high stresses and asymmetry deformations that generate cracking in some weak joints once heated. Therefore, the design default is a primary cause for cracking of the blind vias. • The residue S appearing in the wall interface of the blind vias has a fatal effect on the structural integrity and deposition quality of the copper plating with a formation of CuxS in the interface of copper grains. The structure of CuxS can change with different temperatures, inducing an embrittlement intercrystalline fracture during SMT. Accordingly, the incomplete desmear is the predominant factor for failure of the vias. • An inappropriate reduction in thickness of type 2 PCB and together with the asymmetric configuration of components lead to excessive warpage and deformation of the board, which will generate a big tensile force or a bending stress around pads linked with blind vias. However, under some conditions, cracking will occur in those weak connections of the vias. So, the unsuitable dimension design of the PCB is another potential risk of failure. Suggestions • It is advised that the design of relative locations among pads and components should be optimized through simulation testing including finite element methods (FEM) and bench test. • Meanwhile, the quality inspection on the wall of the blind vias should be emphasized before plating to provide a clean wall surface. • The best thickness of the board should be simulated through FEM and essential property experiments to ensure adequate stiffness of the substrate. Acknowledgment The financial support by both the Shanghai Leading Academic Discipline Project (Project Number: B113) and China Circuit Technology (Shantou) Corporation (CCTC) (Grant SGH2021073) is acknowledged. References 1. Richard, S., Jamal, H., Prado, E.: High-density PWB microvia reliability for space application. Aerosp. Conf. 3–10 March, 2007, IEEE, pp. 1–8 (2007) Fig. 9 SAM inspection of the bare board before and after thermal cycle test. (a) Before testing. (b) After testing. (c) Spectra before testing. (d) Spectra after testing J Fail. Anal. and Preven. (2008) 8:524–532 531 123

J Fail. Anal and Preven.(2008)8: 524-532 2. Martin, P L: Electronic Failure Analysis Handbook, p. 9. Sci. contribution to drop test failures, pp 391-399. 57th ECTC Pro- Press, Beijing (2005)(in Chinese) ceedings (2007) 3. Nishiwaki, T, Mikado, Y, Kuroiwa, N: Comparison of various 9. Marks, M.R.: Novel deprocessing technique for failure analysis micro via technology, pp. 233-237. ISAPM Proceedings(2000) of flip-chip integrated circuit packages. Pract. Fail. Anal. 1(6). 4. Leung, E.S. W, Yung, w.K.C., Lee, W.B.: A study of microvias 45-5202001) produced by laser-assisted seeding mechanism in blind via hole 10. Ji, L-N, Liu, J.S., Yang, Z -G: Failure analysis of BGA solder plating of printed circuit board. Int. J. Adv. Manuf. TechnoL. joint in PCB for novel mobile phones. Heat Treat Met. 32(sup- 24(7-8),74484(2004) pl ) 373-376(2007)(in Chinese with English abstract) 5. Wang, T.H., Lai, Y.S.: Stress analysis for fracturing potential of ll. Christie, D: A review of the science and art of visual examination blind via in a build-up substrate. Circ. World 32(2), 39-44 in failure analysis. J. Fail. Anal. Prevent. 6(3), 1547-7029(2006) (2006) 2. Butron-Guillen, M.P., Cabanas-Moreno. JG. Weertman, J.R 6. Liu. F, Lu, J, Sundaram, V. Sutter, D, White, G. Baldwin, D. Scr. Metall. 24. 991(1990) Tummala, R.R.: Reliability assessment of microvias in HDI 13. Boulliard, J.C., Sotto, M. P: Surf. Sci. 195, 255-269(1988) printed circuit boards, pp. 1159-1163. 5lst ECTC Proceedings 14. Korzhavyi, P A, et al. Theoretical investigation of sulfur solu- 2001) ility in pure copper and dilute copper-based alloys. Acta Mater 7. Ramakrishna. G. Liu. F. Sitaraman. S.K. Role of dielectric 47(5),1417-1424(1999 material and geometry on the thermo-mechanical reliability of 15. Kothari, R, Vook, R.W.: Enhanced sulfur segregation in plasti microvias, pp 439-445. 52nd ECTC Proceedings(2002) ally deformed OFHC Cu and the effect of surface segregated 8. Xie, D, Wang, J, Yu, H, Lau, D, Shangguan, D: Impact sulfur on electric contact resistance. IEEE TCPMT, Part A 17(1), formance of microvia and buildup layer materials and 12l-127(1994) 2 Springer

2. Martin, P.L.: Electronic Failure Analysis Handbook, p. 9. Sci. Press, Beijing (2005) (in Chinese) 3. Nishiwaki, T., Mikado, Y., Kuroiwa, N.: Comparison of various micro via technology, pp. 233–237. ISAPM Proceedings (2000) 4. Leung, E.S.W., Yung, W.K.C., Lee, W.B.: A study of microvias produced by laser-assisted seeding mechanism in blind via hole plating of printed circuit board. Int. J. Adv. Manuf. Technol. 24(7–8), 74–484 (2004) 5. Wang, T.H., Lai, Y.S.: Stress analysis for fracturing potential of blind via in a build-up substrate. Circ. World 32(2), 39–44 (2006) 6. Liu, F., Lu, J., Sundaram, V., Sutter, D., White, G., Baldwin, D., Tummala, R.R.: Reliability assessment of microvias in HDI printed circuit boards, pp. 1159–1163. 51st ECTC Proceedings (2001) 7. Ramakrishna, G., Liu, F., Sitaraman, S.K.: Role of dielectric material and geometry on the thermo-mechanical reliability of microvias, pp. 439–445. 52nd ECTC Proceedings (2002) 8. Xie, D., Wang, J., Yu, H., Lau, D., Shangguan, D.: Impact performance of microvia and buildup layer materials and its contribution to drop test failures, pp. 391–399. 57th ECTC Proceedings (2007) 9. Marks, M.R.: Novel deprocessing technique for failure analysis of flip-chip integrated circuit packages. Pract. Fail. Anal. 1(6), 45–52 (2001) 10. Ji, L.-N., Liu, J.-S., Yang, Z.-G.: Failure analysis of BGA solder joint in PCB for novel mobile phones. Heat Treat. Met. 32(suppl.), 373–376 (2007) (in Chinese with English abstract) 11. Christie, D.: A review of the science and art of visual examination in failure analysis. J. Fail. Anal. Prevent. 6(3), 1547–7029 (2006) 12. Butron-Guillen, M.P., Cabanas-Moreno, J.G., Weertman, J.R.: Scr. Metall. 24, 991 (1990) 13. Boulliard, J.C., Sotto, M.P.: Surf. Sci. 195, 255–269 (1988) 14. Korzhavyi, P.A., et al.: Theoretical investigation of sulfur solubility in pure copper and dilute copper-based alloys. Acta Mater. 47(5), 1417–1424 (1999) 15. Kothari, R., Vook, R.W.: Enhanced sulfur segregation in plastically deformed OFHC Cu and the effect of surface segregated sulfur on electric contact resistance. IEEE TCPMT, Part A 17(1), 121–127 (1994) 532 J Fail. Anal. and Preven. (2008) 8:524–532 123

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