R,z .0000车000 Q00022w Off-Chip Fig.2.Traditional CCC LNA. Fig.3.Proposed LNA schematic actual NF of Fig.2 is still higher than 3 dB for a typical 4kTyl9m⊙ M' 4/3 because of the noise contribution of Rs1.2 and RL1.2.The 之12gm other drawback is that Rs1.2 reduced the voltage headroom and therefore reduced the linearity. v生年v M A DC-coupled balun+LNA topology is proposed to over- 2y. -0000200— come these problems,as shown in Fig.3.The two balanced ports of a transformer-type balun are directly connected to the source of M and M2 respectively,with the center-tapped port grounded providing DC-bias for the LNA.The first advantage (a) of this topology is that the source resistor Rs1.2 and the off- chip AC-coupled capacitors can be removed,while the S-D transform function still remains.The load resistor RL1.2 is 4kT/9-包 12g replaced by NMOST M3.4 for two reasons:1)The linearity can be improved due to a"post-correction"approach [4]:2) NMOS loading with extra AC paths Ca-Ra and Ca-Ra can improve the voltage gain and provide an extra noise-canceling Q00000①-①Hl: 2v joL path [5].From Fig.3,it can be shown that there are now three noise-canceling paths(in dot lines)which are: 1)The CCC path C1-R1 and CS stage M2.Un.ip is AC- coupled to the gate of M2 by C1-R1,and then amplified to (b) Un.on by CS stage M2. 2)The balanced ports of the balun and CG stage M2.Unp is Fig.4.A 1:1 balun model.(a)Original model.(b)De-coupled equivalent transformer-coupled to vn.in by the balun,and then amplified circuit. to Un,on by CG stage M2. 3)The extra feed-forward path Ca-Ra and source follow stage M3.Un.ip is AC-coupled to the gate of M3 by C3-R3. The voltage gain is and then followed toby source follow stage M3. Av =1+2gm1/gm3 (3) With these noise-canceling paths,the output differential- mode noise of Mi.2 is remarkable reduced,therefore the NF where the term "1"comes from the feed-forward paths C3- can be very low. R3-M3 and C4-R4-M4. In order to calculate the noise contribution of M.the balun III.PARAMETER CALCULATION impedance characteristic should be analyzed firstly. In this design,we choose a balun with the impedance ratio A.Balun Model 1:1.The differential input impedance of the LNA is 1/gm,so the input impedance matching condition is When the noise voltage of Mi adds to one of the balanced ports,the balun model can be shown in Fig.4(a).For the 1:1 9m=1/Rs (2)balun,the coil ratio is 2:1 and three inductors LL satisfy 92RL1 Vdd RL2 Vb M1 M2 C1 C2 RS1 RS2 RS S v Off-Chip ni R2 R1 IP IN RFin RFout OP ON n op , v n ip, v n on , v Fig. 2. Traditional CCC LNA. R3 Vdd R4 Vb M1 M2 C1 C2 RS S v Off-Chip C3 C4 R2 R1 M3 M4 n i RFin n op , v n ip, v RFout n on , v n in, v Fig. 3. Proposed LNA schematic. actual NF of Fig. 2 is still higher than 3 dB for a typical γ = 4/3 because of the noise contribution of RS1,2 and RL1,2. The other drawback is that RS1,2 reduced the voltage headroom and therefore reduced the linearity. A DC-coupled balun+LNA topology is proposed to over￾come these problems, as shown in Fig. 3. The two balanced ports of a transformer-type balun are directly connected to the source of M1 and M2 respectively, with the center-tapped port grounded providing DC-bias for the LNA. The first advantage of this topology is that the source resistor RS1,2 and the off￾chip AC-coupled capacitors can be removed, while the S-D transform function still remains. The load resistor RL1,2 is replaced by NMOST M3,4 for two reasons: 1) The linearity can be improved due to a “post-correction” approach [4]; 2) NMOS loading with extra AC paths C3-R3 and C4-R4 can improve the voltage gain and provide an extra noise-canceling path [5]. From Fig. 3, it can be shown that there are now three noise-canceling paths (in dot lines) which are: 1) The CCC path C1-R1 and CS stage M2. vn,ip is AC￾coupled to the gate of M2 by C1-R1, and then amplified to vn,on by CS stage M2. 2) The balanced ports of the balun and CG stage M2. vn,ip is transformer-coupled to vn,in by the balun, and then amplified to vn,on by CG stage M2. 3) The extra feed-forward path C3-R3 and source follow stage M3. vn,ip is AC-coupled to the gate of M3 by C3-R3, and then followed to vn,op by source follow stage M3. With these noise-canceling paths, the output differential￾mode noise of M1,2 is remarkable reduced, therefore the NF can be very low. III. PARAMETER CALCULATION In this design, we choose a balun with the impedance ratio 1:1. The differential input impedance of the LNA is 1/gm, so the input impedance matching condition is gm = 1/RS (2) RS 2:1 2:1 Rip v 2v v 1/ 2gm Rin L1 L2 L3 M M M ' 4 m1 kT g J (a) 1 i 2i 3 i 1 j LZ 2v v v 2 j Mi Z 3 j Mi Z 2 j LZ 3 1 j LZ j Mi Z 1 jZM i' 3 jZM i' 2 j Mi Z RS Rip 1/ 2gm Rin 4 m1 kT g J (b) Fig. 4. A 1:1 balun model. (a) Original model. (b) De-coupled equivalent circuit. The voltage gain is AV =1+2gm1/gm3 (3) where the term “1” comes from the feed-forward paths C3- R3-M3 and C4-R4-M4. In order to calculate the noise contribution of M1, the balun impedance characteristic should be analyzed firstly. A. Balun Model When the noise voltage of M1 adds to one of the balanced ports, the balun model can be shown in Fig. 4(a). For the 1:1 balun, the coil ratio is 2:1 and three inductors L1∼L3 satisfy 92