J.Semicond.2011,32(2) Yin Rui et al. Fig.3.Wide-swing bias circuit of the shared opamp. S-A Φ1D 2D S-B 1D Φ2D 2D Φ1 9Φ1Dn Φ1D 2 sub sub sub sub ADC DAC ADC DAC n.b 2D Φ1 Φ1D Φ1D 2D C 1D 2D Fig.4.Proposed opamp-sharing MDAC small invariable resistance and will not affect the performance period of 1Dn and 2Dn,the opamp is working on dual- of the shared opamp. input-on mode.During this time,both pairs of input are active and have a half current,but are still in saturation.When 2D 3.2.Dual-input MDAC is high,the signal pathway is on.Meanwhile,Vinp,b and Vim.b are disabled since 2Dn goes low,Vinp.a and Vn.a are the only The proposed 1.5-bit opamp-sharing MDAC using the active inputs and the opamp is working on holding mode for switch-embedded amplifier is shown in Fig.4.When I is stage-A. high,both Vinp.a and Vinn,a are connected to the common-mode input voltage Viem for resetting.When ID is high,the sam- Since both input pairs are reset to a common-mode input pling switches are on and Cia and C2a sample the input signal voltage alternately,the memory effect is completely eliminated for stage-A while the opamp is working on holding mode for without needing any additional clock phase.Furthermore,the stage-B.At the end of the sample process,1 turns to low be- opamp-sharing switches are embedded into the opamp instead foreΦlD,which is so called“bottom plate sampling”.At the of in series between the sampling capacitors and the opamp moment after the bottom plate sampling switch is completely inputs,therefore the crosstalk path is avoided.In addition, off and the previous signal is still holding,the sub-ADC com- since the opamp-sharing switches do not connect directly to pares the result,passes the 2-bit digital codes to the sub-DAC the opamp input transistors,the charge injection and the signal- and the digital error correction module.During the overlapping dependent resistance do not exist for the same reason. 025006-3J. Semicond. 2011, 32(2) Yin Rui et al. Vnc Vpc Vb3 Vicm VDD VDD I ref1 I ref2 Vb4 Vb1 Vb2 VSS Fig. 3. Wide-swing bias circuit of the shared opamp. sub DAC Φ1Dn Φ2Dn C1a C3a Φ1D Φ1D Φ2D Vinp C2a C4a Φ1D Vinn Vicm Φ1 Φ1 Voutp Voutn Vinp, a Vinn, b Vinn, a C1b C3b Φ2D C2b C4b Φ2D Φ2 Φ1D Φ2D S-A S-B Φ2D Φ2D Φ1D Φ1D sub ADC sub DAC sub ADC Vicm Φ2 Vinn, b V Vinp, b inp, b Fig. 4. Proposed opamp-sharing MDAC small invariable resistance and will not affect the performance of the shared opamp. 3.2. Dual-input MDAC The proposed 1.5-bit opamp-sharing MDAC using the switch-embedded amplifier is shown in Fig. 4. When ˆ1 is high, both Vinp; a and Vinn; a are connected to the common-mode input voltage Vicm for resetting. When ˆ1D is high, the sam￾pling switches are on and C1a and C2a sample the input signal for stage-A while the opamp is working on holding mode for stage-B. At the end of the sample process, ˆ1 turns to low be￾fore ˆ1D, which is so called “bottom plate sampling”. At the moment after the bottom plate sampling switch is completely off and the previous signal is still holding, the sub-ADC com￾pares the result, passes the 2-bit digital codes to the sub-DAC and the digital error correction module. During the overlapping period of ˆ1Dn and ˆ2Dn, the opamp is working on dual￾input-on mode. During this time, both pairs of input are active and have a half current, but are still in saturation. When ˆ2D is high, the signal pathway is on. Meanwhile, Vinp; b and Vinn; b are disabled since ˆ2Dn goes low, Vinp; a and Vinn; a are the only active inputs and the opamp is working on holding mode for stage-A. Since both input pairs are reset to a common-mode input voltage alternately, the memory effect is completely eliminated without needing any additional clock phase. Furthermore, the opamp-sharing switches are embedded into the opamp instead of in series between the sampling capacitors and the opamp inputs, therefore the crosstalk path is avoided. In addition, since the opamp-sharing switches do not connect directly to the opamp input transistors, the charge injection and the signal￾dependent resistance do not exist for the same reason. 025006-3