J.Semicond.2010,31(7) Meng Lingbu et al. 1. can be easily integrated.A conventional tri-state deadzone free phase-frequency detector(PFD)is employed here.The charge 1.2 pump with common-mode feedback is also differential and can achieve excellent current match.Programmed P/S counters and 1.0 8/9 prescaler is used for the multi-modulus divider to obtain 兰0.8 the desired division ratio.A retiming circuit is used to lower the phase noise from the divider. 0.6 3.1.Charge pump 0.4 Charge pump with high linearity is desirable in the CP- 0.2 PLL.The nonideal effects such as leakage current and the current mismatch can cause not only the deterioration of the reference spur but also degradation of in-band phase noise 0 10 20 30 Time(μs) in fractional-N mode.Fully-differential charge pump is often prior in that it achieves a higher linearity.Additionally,differ- Fig.3.PLL locking time simulation. ential charge pump can effectively suppress the common-mode noise from the power supply and substrate. A modified fully-differential charge pump from Ref.[8] -60 is shown in Fig.6.The positive and negative branches of the fully-differential charge pump are the left and right cir- -80 cuits respectively.For simplicity,only the positive circuit is considered.Transistors M1,M3,M6,M9 compose a replica -100 PLL circuit.M4 and M7 are switches which control whether the DIVIDER charge pump is open or not.The additional MOS branches 120 CP composed by transistors M5 and M8 and the added capacitance Reference Cs are combined to stabilize the common source nodes A and C.Operational amplifier Al is configured as buffer to ensure 140 M5 and M8 working properly when charge pump is closed. SDM By using an error amplifier A3,the voltage Vopc follows the -160 10 voltage Vop.If (W/L)1=(W/L)2,(W/L)3 =(W/L)4, 109 10p Frequency Offset(Hz) (WL)6 =(W/L)7 and (W/L)9 =(W/L)10,current flow- ing through M3 will be equal to that flowing through M4 and Fig.4.PLL phase noise simulation because the transistor in the two path are matched.At the same time.current flowing through M6 will be equal to that flowing through M7.So the sinking current equals the sourcing current. In this way,current matching characteristics can be obtained regardless of the variation of output controlling voltages All of the transistors except the dummy transistors PFD (M11-M14)work in the saturation region.One notable advan- dnb tage is that transistors working in the saturation region are of smaller gate-to-drain capacitance Ced than transistors working Differential LPF in the linear region;another advantage is that the saturation Differential CP transistors have a faster speed.The operational amplifiers in the charge pump only need a bandwidth comparable with the p/s 89 prescaler loop bandwidth of the PLL so as to respond in time to the vari- ation at the output nodes.What is more,the load of these oper- ational amplifiers is only the parasitic capacitance of the tran- SDM sistors which is quite small.As a result,the four operational amplifiers employed in the charge pump consume only limited Fig.5.Block diagram of the 2-2.4 GHz fractional-N frequency syn- power. thesizer The signals from PFD toggle between VSS and VDD and are not suitable to switch these transistors working in satura- 3.Circuit design tion region directly.Thus a level shift is needed to convert the rail-to-rail signals from PFD output to the targeted analog sig- The presented 2-2.4 GHz differentially-tuned fractional-N nals.Figure 7 illustrates the simplified partial level shift cir- frequency synthesizer is shown in Fig.5.For this differentially- cuits used in the charge pump.After the level shift the analog tuned architecture,the big capacitor C in loop filter is ex- control signals can be obtained.Besides,the switches in the actly half that in single-ended frequency synthesizer so that the level shift are connected to a moderate resistance so as to make loop filters transfer function keep unchanged compared with the complementary control signals UP,UP-more symmetrical that in single-ended architecture.By this way the loop filter so as to effectively reduce the high speed glitchs] 075007-3J. Semicond. 2010, 31(7) Meng Lingbu et al. Fig. 3. PLL locking time simulation. Fig. 4. PLL phase noise simulation. Fig. 5. Block diagram of the 2–2.4 GHz fractional-N frequency syn￾thesizer. 3. Circuit design The presented 2–2.4 GHz differentially-tuned fractional-N frequency synthesizer is shown in Fig. 5. For this differentially￾tuned architecture, the big capacitor C1 in loop filter is ex￾actly half that in single-ended frequency synthesizer so that the loop filters transfer function keep unchanged compared with that in single-ended architecture. By this way the loop filter can be easily integrated. A conventional tri-state deadzone free phase-frequency detector (PFD) is employed here. The charge pump with common-mode feedback is also differential and can achieve excellent current match. Programmed P/S counters and 8/9 prescaler is used for the multi-modulus divider to obtain the desired division ratio. A retiming circuit is used to lower the phase noise from the divider. 3.1. Charge pump Charge pump with high linearity is desirable in the CP￾PLL. The nonideal effects such as leakage current and the current mismatch can cause not only the deterioration of the reference spur but also degradation of in-band phase noise in fractional-N mode. Fully-differential charge pump is often prior in that it achieves a higher linearity. Additionally, differ￾ential charge pump can effectively suppress the common-mode noise from the power supply and substrate. A modified fully-differential charge pump from Ref. [8] is shown in Fig. 6. The positive and negative branches of the fully-differential charge pump are the left and right cir￾cuits respectively. For simplicity, only the positive circuit is considered. Transistors M1, M3, M6, M9 compose a replica circuit. M4 and M7 are switches which control whether the charge pump is open or not. The additional MOS branches composed by transistors M5 and M8 and the added capacitance Cs are combined to stabilize the common source nodes A and C. Operational amplifier A1 is configured as buffer to ensure M5 and M8 working properly when charge pump is closed. By using an error amplifier A3, the voltage VOPC follows the voltage VOP. If (W =L/1 D .W=L/2, (W=L/3 D .W =L/4, (W =L/6 D .W =L/7 and (W =L/9 D .W =L/10, current flow￾ing through M3 will be equal to that flowing through M4 and because the transistor in the two path are matched. At the same time, current flowing through M6 will be equal to that flowing through M7. So the sinking current equals the sourcing current. In this way, current matching characteristics can be obtained regardless of the variation of output controlling voltages. All of the transistors except the dummy transistors (M11–M14) work in the saturation region. One notable advan￾tage is that transistors working in the saturation region are of smaller gate-to-drain capacitance Cgd than transistors working in the linear region; another advantage is that the saturation transistors have a faster speed. The operational amplifiers in the charge pump only need a bandwidth comparable with the loop bandwidth of the PLL so as to respond in time to the vari￾ation at the output nodes. What is more, the load of these oper￾ational amplifiers is only the parasitic capacitance of the tran￾sistors which is quite small. As a result, the four operational amplifiers employed in the charge pump consume only limited power. The signals from PFD toggle between VSS and VDD and are not suitable to switch these transistors working in satura￾tion region directly. Thus a level shift is needed to convert the rail-to-rail signals from PFD output to the targeted analog sig￾nals. Figure 7 illustrates the simplified partial level shift cir￾cuits used in the charge pump. After the level shift the analog control signals can be obtained. Besides, the switches in the level shift are connected to a moderate resistance so as to make the complementary control signals UP, UP– more symmetrical so as to effectively reduce the high speed glitchŒ8 . 075007-3