SRAM:cMOs存髓阜元 SRAM:cMOS存储草元 逻辑表达 A+X D 不D ■大量,电路力求简化——反相器、传输门并接 ■Q在以下条件下为1 “A=0且“不出现(=1D=0)” A-X.D=d+X D Synchronous SRAM(SSRAM) Special sRAM ■ Use latch- ype SRAM cells internally ■单端口SRAM n Put registers in front ■双端口SRAM SAM of address and control (and maybe data)for 双口 RAM DPRAM easier interfacing with SAM(Sequential Access Memory) synchronous systems FIFO(First-In First-Out)标识位 at high speeds FILO ■Eg. Pentium cache RAMS ICAM(Content Addressed Memory) 2动态RAM Ref. 10.4 DRAM-chip internal organization 256X256 ■S闭合 ■S断开 增加开关S,定时闭合—刷新3 19 SRAM: CMOS存储单元 „大量，电路力求简化——反相器、传输门并接 „ Q在以下条件下为1 “A=0”且“不出现(X=1,D=0)” +VDD T1 T2 A Q D TN X Q X D A Q = A⋅ X ⋅ D = A + X ⋅ D 20 SRAM: CMOS存储单元 „ Q逻辑表达 X D Q Q X D A Q A XD = + ⋅ 21 „ Use latch-type SRAM cells internally „ Put registers in front of address and control (and maybe data) for easier interfacing with synchronous systems at high speeds „ E.g. Pentium cache RAMs Synchronous SRAM(SSRAM) Synchronous SRAM(SSRAM) 22 Special SRAM „单端口SRAM „双端口SRAM 双口RAM DPRAM SAM(Sequential Access Memory) FIFO(First-In First-Out) FILO „CAM(Content Addressed Memory) Ii SAM Oi 写入 读出 标识位 23 2.动态RAM Ref. 10.4 „ SD闭合 „ SD断开 增加开关SH，定时闭合——“刷新” D 1 C SH SD 24 64K x 1 DRAM DRAM-chip internal organization