《数字电子技术》课程教学课件（PPT讲稿）第三章 组合逻辑电路 CH38 组合逻辑电路的 VHDL 描述及其仿真

LRR△RYIEEE: decoder38.scf-Waveform Editor ▣x Ref 0.0ns 中 Time:404.0ns Interval: 404.0ns 0.0ns Name: 50.0ns 100.0ns 150.0ns 200.0ns 250.0ns 300.0ns 350.0ns 400.01 a 000 001 010 011 100 101 110 111 00000001 00000010 00000100 00001000 00010000 00100000 01000000: 10000000 PROCESS(a) BEGIN CASE a IS WHEN"000'=>yyyyyyyynull; END CASE; END PROCESS: END one;

[ 例3 .8 .1 ] 3线-8线译码器的VHDL描述及仿真 3. 8 组合逻辑电路的VHDL 描述及其仿真 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY decoder38 IS PORT(a : IN STD_LOGIC_VECTOR(2 DOWNTO 0); y: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END decoder38; ARCHITECTURE one OF decoder38 IS BEGIN PROCESS (a) BEGIN CASE a IS WHEN "000" => y y y y y y y ynull ; END CASE; END PROCESS; END one;

encoder83.scf-Waveform Editor -▣x Ref:401.0ns 1+中Time:148.0ns Interval: 253.0ns 401.0ns Name: Value: 100.0ns200.0ns300.0ns4000ns500.0ns600.0ns700.0ns800.0ns900.0ns -d7 1 工=d6 0 -d5 0 -d4 0 -d3 0 -d2 0 =d1 0 encode B000 1111101011000110100010001110101011000110100010001111101016 y "110"when d(6)='1'else "101"when d(5)='1'else "100"when d(4)='1'else "011"when d(3)='1'else "010"when d(2)='1'else "001"when d(1)='1'else "000"when d(0)='1'; END one;

[例LIBRARY IEEE; 3 .8 .2 ] 8线-3线优先编码器的 VHDL 描述及仿真 USE IEEE.STD_LOGIC_1164.ALL; ENTITY encoder83 IS PORT( d : IN STD_LOGIC_VECTOR(7 DOWNTO 0); encode: OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); END encoder83; ARCHITECTURE one OF encoder83 IS BEGIN encode <= "111" when d(7) = '1' else "110" when d(6) = '1' else "101" when d(5) = '1' else "100" when d(4) = '1' else "011" when d(3) = '1' else "010" when d(2) = '1' else "001" when d(1) = '1' else "000" when d(0) = '1' ; END one;

nA mux41.scf-Waveform Editor -▣x Ref:0.0ns ▣Time:334.0ns Interval: 334.0ns 0.Ons Name: Value: 100.0ns200.0ns300.0ns400.0ns500.0ns600.0ns700.0ns600.0ns900.0ns1.c 工-d 0 工-c 0 工-b 0 0 B00 00X01X10X11X00X01X10X11X00X01X10X11X00X01X10X11X00X01X10X11 0 BEGIN CASE s IS WHEN"00"=>zzZzZ<='x'; END CASE; END PROCESS; END one;

[例 3 .8 .3 ] 4 选 1 数据选择器的VHDL 描述及仿真 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux41 is PORT (a,b,c,d : IN STD_LOGIC; s : IN STD_LOGIC_VECTOR(1 DOWNTO 0); z : OUTSTD_LOGIC); END mux41; ARCHITECTURE one OF mux41 IS BEGIN PROCESS (s ,a,b,c,d) BEGIN CASE s IS WHEN "00" => z z z zz<= 'x'; END CASE; END PROCESS; END one;