Review-IARMIntroduction AboutProductsDevelopMarketsARM022019/3/3
Review - I ARM Introduction About Products Develop Markets ARM02 2019/3/3 1
ARMIARMIntroductionIlARMArchitecture III Exynos4412 SoCIV EmbeddedLinuxVAndroidSystem VIApplication DesignARM022019/3/3
ARM ARM02 2019/3/3 2 I ARM Introduction II ARM Architecture III Exynos4412 SoC IV Embedded Linux V Android System VI Application Design
IARMArchitectureARMArchitectureReferenceMgnuglforARMv8-AarchitectureprofileARMLimitedARM Architecture Reference ManualARMv8,forARMv8-AarchitectureprofiARM022019/3/3
II ARM Architecture ARM02 2019/3/3 3 ARM Architecture Reference Manual for ARMv8-A architecture profile ARM Limited
IlARMArchitecture(cont)HCD-0nCerbeARMThe Architecture for the Digital WorldWatcone HionggutuseeProoletotProductsSupportGonMaketAbou-[Seardh our documentationAlldocumentssarchscose:.AlltopicContent:ARNarchitectur中明品口About thissiteARMvB-AReference Manual(issueA.c)siteFAQsCiving feedbackARMGlosSarYARMvS-AReferenceManualgeArticPARMTechnicalSupportKno(Issue A.c)BARMarcitectusReereThisdoowCisory wsiaute In aPDFversiontoregisteredARMcustomersonSetOvervieiCopyrightC 2014ARM Limited.Al rights reserved.ARHDD10487A.Cual(1sstNon-Conifidential Restricted AccessPDFverslon0HanotARiv5ReferenceMartimGlBnstnucton Set QuickRaferenceCardsE3SystemArchitectur#azelle Coresight and ETM Architesture SpecificationARtGenaricIntermuptControllerArchitectureSystemMemoryHanament Unit ArchitectievelopmenttoolsPKeilembeddeddevelopmenttoolsDevelnpmentboardand ArtidevelopeandTutoriabndoFeedlbaciARM022019/3/3
II ARM Architecture (cont) ARM02 2019/3/3 4
IlARMArchitecture(cont) A ArchitectureIntroductionBTheAArch64ALACTheAArch64ISDTheAArch64SLAETheAArch32ALAFTheAArch32ISGTheAArch32SLAHExternal DebugIMemory-mappedComponentsJAppendixesARM022019/3/3
II ARM Architecture (cont) ARM02 2019/3/3 5 A Architecture Introduction B The AArch64 ALA C The AArch64 IS D The AArch64 SLA E The AArch32 ALA F The AArch32 IS G The AArch32 SLA H External Debug I Memory-mapped Components J Appendixes
Conventions TypographySignalsNumbersPseudocode Assembler syntaxARM022019/3/3
Conventions ARM02 2019/3/3 6 Typography Signals Numbers Pseudocode Assembler syntax
Conventions-Typographyitalic:terms &citationsbold:signal names,inlistmonospace:assembler&pseudocode SMALL CAPITALS: terms, both in body & glossary口colored text:link,inbluecolorARM022019/3/3
Conventions - Typography ARM02 2019/3/3 7 italic: terms & citations bold: signal names, in list monospace: assembler & pseudocode SMALL CAPITALS: terms, both in body & glossary colored text: link, in blue color
6XDol0487ADarmv8_arm.pdf-AcobeAcrobatPro模图M)度口(W)美站（H)文件(F）弹锁（E)D88OOD0D0?创建工具注释共字00/5242OO+4%E图16通Aboutthismanual一ThismaualdesoibestioARMarchitcturev8,ARMv.ThearchitcturedescrbestheoperationofanARMvsProcessing element (PE)d this manual includesdescriptions of?The two Executione5. AArch64 and AArch32.EThe instruction sets:In AArch32 state, the Asuction sets, that are compatible with earlier versions oftheARM architectureIn AArch64 state, theitalic:terms &citationsThe states that determine horAArch32 state the PE modeThe Exception modelThe interprocessing model.that supports transitioning between AArch64 state and AArch32 stateThe memory model, that defines memory orderine armamal coversa singlearchitecture profile.ARMv8-A, thatdefiCa Vrtual Memory SystemArchitechure (VMSA)The programmers’ model. and its interfaces to System registers that control most PE and memory systemfeatures. and provide status information.The Advanced SIMD and floating-point instructions, that provide high-perfomance:8Single-precision and double-precision floating-point operations
8 ARM02 2019/3/3 italic: terms & citations
6XDol487ADarmv8_arm.pdf-AcobeAcrobatPro模图M)度口（W)我站（H)文件(F）弹锁（E)口B880OODDA?创建t1712/5242AO+4%图工具注释共字-画TableD4-32Accesspermissionsfor instruction execution,EL2andEL3translation regimes吧SCTLR EL2.WXNo1XNAP[2]AccessfromEL2orEL3SCTLREL3.WXNO000ExecutableENot execuitablec1Executable1xbold:signalnames,inlista.SeeTableD4-28 on pageD4.b..SCTLREL2fortheEL2translac.Not executable because of the SCTLR ELx WXN control_ because region is writable at this Exception level.Instructionexecutionpermissionsforstage2translationsFor the Non-secure ELI&0 stage 2 translation,theXN bit in the stage 2 translation table descriptors controls theexecution pemission, and this control is completely independent of the S2AP access pemissions.TableD4-33Accesspermissionsfor instructionexecutionforstage2oftheNon-secureEL1&0translationregime,XNAccessfromNon-secureEL1orNon-secureELo
9 ARM02 2019/3/3 bold: signal names, in list
四-6XDol0487ADarmv8_arm.pd-AcobeAcrobatPro文件（F）鼻辅（E)模图M)宽口(W)我站(H)L口国880创建OOODAA0O+143%日图工具注释共字00112/5242画ExampleC1-1ADD instructions withdifferentopcodesADD WO, W1, W2// add 32-bit register?ADD X0, X1, X2// add 64-bit registerADD X0, X1, W2, SXTW// add 64-bit extended register5ADD X0,X1,#42// add 64-bit immediatC1.2.3Condition Codeflags or test condition codes or both.For information aboutThe A64 ISA has some instructions thainstructions that set thecondition flags orusewemonics,seeConditionflagsandrelatedinstructionson page C6-386Table C1-l shows the available cormonospace:assemblerTable C1-1Condition codescondMnemonicCondition flagsMeaning(integerMeaning (floating-point)EQEqualZ=1000EqualNE0001Not equalNot equal or unorderedZ=0100010CS or HSC=1Carry setGreater than,equal.,or unordered0011rcor10CarrclaaIaontho^
10 ARM02 2019/3/3 monospace: assembler