Review-Exynos4412SoCB口9INTERRUPT1口10INTERRUPT224 TIMER 25 MCT 26 WD27 RTCARM092019-4-9
Review – Exynos4412 SoC B ARM09 2019-4-9 1 9 INTERRUPT1 10 INTERRUPT2 24 TIMER 25 MCT 26 WD 27 RTC
IIExynos4412SoCC28UART口29 12C口30SPI口31 USB1口32USB2口33TSI口34AUDIO口35IIS1口36lIS2口37AC97口38PCM口39SPDIF口ARM092019-4-9
III Exynos4412 SoC C 28 UART 29 I2C 30 SPI 31 USB1 32 USB2 33 TSI 34 AUDIO 35 IIS1 36 IIS2 37 AC97 38 PCM 39 SPDIF ARM09 2019-4-9 2
IIExynos4412SoCC口40C2C41HSI口42DISPLAY口43CAMERA口44FIMCLITE口45MIPI1口46MIPI2口47G2D口口48G3D49ROTATOR口50JPEGARM092019-4-9
III Exynos4412 SoC C ARM09 2019-4-9 3 40 C2C 41 HSI 42 DISPLAY 43 CAMERA 44 FIMC_LITE 45 MIPI1 46 MIPI2 47 G2D 48 G3D 49 ROTATOR 50 JPEG
IIExynos4412SoCC51MFC52VIDEO口53MIXER口54HDMI口55SSS口56KEYPAD口57ADC口58TMU口59FIMC-IS口60DATA161DATA2ARM092019-4-9
III Exynos4412 SoC C ARM09 2019-4-9 4 51 MFC 52 VIDEO 53 MIXER 54 HDMI 55 SSS 56 KEYPAD 57 ADC 58 TMU 59 FIMC-IS 60 DATA1 61 DATA2
28 UART
28 UART
Peripheral BUSTransmitterTransmit FIFO Register(FIFO mode)Transmit Buffer RegisterTransmitHoldingRegister(Non-FIFO mode)Transmit Shifter★ TXDn---.ControlBuad-rateClock SourceUnitGeneratorReceiverMS+RXDnReceive ShifteramsungReceive Holding Register(Non-FIFO mode only)Receive Buffer RegisterReceive FIFO Register(FIFO mode)InFIFOmode,allbytesof BufferRegisterareusedasFIFOregister.In non-FIFO mode, only 1 byte of Buffer Register is used as Holding register.6ARMO92019-4-9Figure 28-1BlockDiagramofUART
6 ARM09 2019-4-9
2912CInter-lntegrated Circuit
29 I2C Inter-Integrated Circuit
2912C 29.1 Overview29.2 Features29.3BlockDiagram 29.4 Interface Operation29.51/ODescription29.6 RegisterDescription 29.7 Touch Screen29.8 SummaryARM092019-4-9
29 I2C ARM09 2019-4-9 8 29.1 Overview 29.2 Features 29.3 Block Diagram 29.4 Interface Operation 29.5 I/O Description 29.6 Register Description 29.7 Touch Screen 29.8 Summary
29.1OverviewARM092019-4-9
29.1 Overview ARM09 2019-4-9 9
12CADDAddressRegister全ComparatorI2C-BusControl Logic全SCL12CCON12CSTATShiftRegisterPCLKSDA4-bitPrescaler全ShiftRegister(2CDS)全Data BusFigure29-1I2C-BusBlockDiagramExynoshasfourI2CbusinterfacesArbitration controls multi-master/slave transferMaster cores initiate/terminate data transfer10ARM092019-4-9
10 ARM09 2019-4-9 I2CADD Exynos has four I2C bus interfaces Arbitration controls multi-master/slave transfer Master cores initiate/terminate data transfer