Network-on-Chif (2/2) Ben abdallah abderazek The University of Aizu E-mail: benab@u-aizuac jp Hong Kong University of Science and Technology, March 2013
Network-on-Chip (2/2) Ben Abdallah Abderazek The University of Aizu E-mail: benab@u-aizu.ac.jp 1 Hong Kong University of Science and Technology, March 2013
Part II: NoC Building Blocks T opolO Routing algorithms Routing Mechanisms Switching Flow Control Router architecture Network Interface
Part II: NoC Building Blocks Topology Routing Algorithms Routing Mechanisms Switching Flow Control Router Architecture Network Interface 2
Part II: NoC Building Blocks T opolO Routing algorithms Routing Mechanisms Switching Flow Control Router architecture Network Interface
Part II: NoC Building Blocks Topology Routing Algorithms Routing Mechanisms Switching Flow Control Router Architecture Network Interface 3
NoC Switching a Switching techniques define the way and time of connections between input and output ports inside a switch a Circuit switched networks reserve a physical path before transmitting the data packets o Packet switched networks transmit the packets without reserving the entire path ng Techniques Circuit switchin Packet Switching Wormhole s&F VⅤ irtual Cut Switching Switchin Through
NoC Switching ❑ Switching techniques define the way and time of connections between input and output ports inside a switch. ❑ Circuit switched networks reserve a physical path before transmitting the data packets ❑ Packet switched networks transmit the packets without reserving the entire path. 4
Circuit Switching Header probe Acknowledgment Data setup data Time Busy Hardware path setup by a routing header or probe End-to-end acknowledgment initiates transfer at full hardware bandwidth
Circuit Switching ❑ Hardware path setup by a routing header or probe ❑ End-to-end acknowledgment initiates transfer at full hardware bandwidth tr ts tsetup tdata Time Busy Header Probe Acknowledgment Data Link ts 6
Circuit Switching Example Configuration Probe Dat Circuit Acknowledgement a Significant latency overhead prior to data transfer a Other requests forced to wait for resources
Circuit Switching Example ❑ Significant latency overhead prior to data transfer ❑ Other requests forced to wait for resources Acknowledgement Configuration Probe Data Circuit 0 5 7
Store forward Switchine Intermediate nodes Destination node ource node Each node along a route waits until a packet is completely received (stored)and then the packet is forwarded to the next node a I wo resources are neede Packet-sized buffer in the switch Exclusive use of the outgoing channel
Store & Forward Switching 9 Source node Intermediate nodes Destination node ❑ Each node along a route waits until a packet is completely received (stored) and then the packet is forwarded to the next node ❑ Two resources are needed ▪ Packet-sized buffer in the switch ▪ Exclusive use of the outgoing channel
Store Forward Switching Example High per-hop latency a Larger buffering required 11
❑ High per-hop latency ❑ Larger buffering required Store & Forward Switching Example 11
Store Forward Switchine OHBBBTI 田BBBT JHBBBT HBBBT 0 10 ycle 口 Advantage While waiting to acquire resources no channels are being held idle Disadvantage Requires a large amount of buffer space at each node Very hi h latency
❑ Advantage ▪ While waiting to acquire resources, no channels are being held idle ❑ Disadvantage ▪ Requires a large amount of buffer space at each node ▪ Very high latency 12 Store & Forward Switching
Virtual Cut-through Switching a transmission on the next channel starts directly when the new header flit is received a Channel is released after tail flit 0 HBBB 2 BIBb 0 10 Cycle
Virtual Cut-through Switching 14 ❑ Transmission on the next channel starts directly when the new header flit is received ❑ Channel is released after tail flit
