2.1 理想开关 2.2 MOSFET开关 2.3 基本的CMOS逻辑门 2.4 CMOS复合逻辑门 2.5 传输门电路 2.6 时钟控制和数据流控制

中国科学技术大学：《超大规模集成电路设计（VLSI）》课程教学资源（设计实验）Cadence IC 设计实验（Diva Interactive Verification）

电子科技大学：《集成电子学 Integrated Electronics》课程教学资源（课件讲稿）第三章 VLSI集成物理（2/2）

电子科技大学：《DSP算法实现技术与架构 VLSI Digital Signal Processing Systems Design and Implementation》课程教学资源（课件讲稿）Chapter 15 数字强度缩减 Numerical Strength Reduction

13.1 Introduction 13.2 Parallel Multipliers 13.3 Interleaved Floor-Plan and Bit-Plane-Based Digital Filters 13.4 Bit-Serial Multipliers 13.5 Bit-Serial Filter 13.6 Canonic Signed Digit Arithmetic

10.1 Introduction 10.2 Pipeline interleaving in digital filters 10.3.1 Pipelining for 1st-Order IIR Filters 10.3.2 Look-Ahead Pipelining with Power-of-2 Decomposition 10.3.3 Look-Ahead Pipelining with General Decomposition 10.4 Pipelining in Higher-order IIR Digital Filters 10.5 Parallel Processing in IIR Filters

8.1 Introduction 8.2 Cook-Toom algorithm 8.3 Winograd algorithm 8.4 Iterated convolution

电子科技大学：《DSP算法实现技术与架构 VLSI Digital Signal Processing Systems Design and Implementation》课程教学资源（课件讲稿）Chapter 06 折叠 Folding

4.1 Introduction 4.2.1 Quantitative description 4.2.2 Properties of retiming 4.3 Solving systems inequalities 4.4 Retiming techniques 4.4.1 Cutset retiming and pipelining 4.4.2 Clock period minimization 4.4.3 register minimization

2.1 Introduction 2.2 Data-flow graph 2.3 Loop bound 2.4.1 LPM 2.4.2 MCM 2.5 MRDFG