复旦大学：微电子工程教学资源（参考论文）ASIC综合后的静态验证方法的研究

FPGA Design Method Design flow & tools Deign Model of Verilog HDL Design style of Verilog HDL Design Examples • RTL level design • Components of Datapath • Components of Controller

Verilog for Verification • Testbench anatomy • Behavioral modeling for Testbench • Some examples Timing specification • Delay model • Timing verification • Pipeline technology Design For Test (DFT) Test vs. Verification Build In Self Test (BIST) Scan and Boundary Scan

Digital Signal Processing • Signal & System • DSP system • Description for DSP FIR Filter Design & Implement • Digital Filter • Specification Design • Hardware Implementation Some Examples • Digital Down Converter • Central Processing Unit

• Synthesizable • Some experiences ➢ Balance architecture ➢ Share resources ➢ Gated signal ➢Assignment statement ➢ Accident / Intentional Latch • Other syntax rules

• Topics Covered • Requirements • Others Info

• History, Present & Future • Manufacturing Process • Some Terms

中科院高能物理研究所：四通道低噪声GEM探测器前端读出ASIC设计（吕继方）

本章首先介绍FPGA/CPLD开 发和ASIC设计的流程，然后分别 介绍与这些设计流程中各环节密 切相关的EDA工具软件，最后就 MAX+plusII的基本情况和EDA 重用模块IP作一简述

一、 历史与现状 二 、EDA技术的基本特征 三 、EDA工具简介 四 、ASIC设计—EDA的重要应用 五 、课程主要内容