复旦大学：《纳米线材料和功能器件》课程教学资料_纳米线电子器件_Logic Gates and Computation from Assembled Nanowire Building Blocks

RESEARCH ARTICLE on assays, cells were immunoblot analysis. For cellular experiments, 29. P Tsao, T. Cao, M. von Zastrow, Trends PharmacoL. doned into pcDNA3. All sequences were confirmed MG132(20 HM)or lactacystin(20 AM) mixed in separated by SDS-PAGE, and the pi with an automated ABI DNA sequencer(Howard 他p计 24. Supplementary Web material is available on Science 4107(1993) 16. P van Kerkhof, R Govers, C M. Alves dos Santos, G.J. Strous, /.Biol. Chem. 275, 1575(2000 www.sciencemagorgcgicontent/full32A.L.Parola,S.lin,B.KKobilka,AnalBiochem.254, gged WT-B2AR and B2AR, along 25. T Buschmann, S Y Fuchs, C-G. Lee, Z-Q Pan, Z. 33. Flag B, ARs expressed in HEK293 cells ently transfected in Rona,ce101.753(2000 in six-well dishes were treated with or without iso- as the substrate in a ubiquitination reaction conta ceptors were labeled with Flag mA ing 20 mM Hepes(PH 7.5). 5 mM MgCI2, 2 mM resolved on SDS-PAGE and probed with antibodies Ub P4D1 and B2AR H-20. hate(ATP). 5 ug of ubiquitin, 20 HM MG132, and secondary antibody. Receptor internalization was 18. W. P. Hausdorff et al., Proc. Natl. Acad. Sci. U.S.A. crude rabbit reticulocyte lysate(RRL, Promega ource for the 150-mm dishes treated or reaction). The reactions were supplemented with ei- 34. O.B. Goodman Jr et al., Nature 383, 447(1996). 2m2635n(1如505A5 (8 ug)or Cos-7 lysate with overexpressed Mdm2 36. S. Mori et al, Eur /. Biochem. 247, 1190(1997) overexpressed B AR, cells seeded at 400,000 per Reaction mixtures we 37. M. Bouvier et al mol phar 100-mm dish were transfected with pcDNA3-Flag- immunoprecipitated using FLAG affinity beads(Sig- for secretarial assistance: B. K. Kobilka fo gation at 250,000g, 45 min. After addition of SDS- ma). Ubiquitinated species were detected with anti 20. C T. Chien, P L Bartel R Sternglanz, S Fields, Proc. 27. A cDNA construct of B-arrestin2 wa NatL. Acad. sci. U.S.A PET-29a and was used to isolate recombinant STAG- F. T. Lin for BarrHis6 constructs: M. Cong for S. Fang ]. P Jensen, R L. Ludwig, K H. Vousden, A.M. iseman,/. Biol. Chem. 275, 8945(2000). providing pcDNA3-P2<: S.J. Perry and KPIerce 22. R. Honda. H. Tanaka. H. Yasuda. FEBs Lett. 420. 25 assistance. Supported by NIH grant DT T, 2 mM ATP, 5 ug of ubiquitin, 20 HM MG132, HL16037. R .L is an investigator of the Howard in LB(10). B-Arrestin was immunoprecipitated from g of Cos cell extract(clarified by centrifugation at ,000g for 15 min) with or without overexpressed 7 June 2001: accepted 17 September 2001 28. K. Nakamura,, M. F. Lazari, S. Li, C. Korgaonkar, M 10.1126/ spence.1063 scoli, Mol. Endocrinol. 13, 1295 (1999). Include this information when citing this paper REPORTS Logic Gates and Computation gies to meet expected computing demands of the future. Bottom-up approaches to nano- from Assembled nanowire electronics(2), where the functional electron- ic structures are assembled from well-defined Building Blocks anoscale building blocks, such as carbon nanotubes (3-8), molecules(9-11),and/or semiconductor nanowires(12-14), have the Yu Huang, Xiangfeng Duan, Yi Cui, ' Lincoln J.Lauhon potential to go far beyond the limits of top- Kyoung-Ha Kim,2 Charles M. Lieber. 2t down manufacturing. For example walled carbon nanotubes (NTs) have Miniaturization in electronics through improvements in established"top-down sed as building blocks to fabricate fabrication techniques is approaching the point where fundamental issues are temperature field-effect transistors (FETs expected to limit the dramatic increases in computing seen over the past several (-5), diodes (6, 7)and recently, an inverter decades. Here we report a"bottom-up"approach in which functional device el- (8), which represents a key component for ements and element arrays have been assembled from solution through the use logic. However, the inability of electronically well-defined semiconductor nanowire building blocks. We show whether NTs are semiconducting or metallic that crossed nanowire p-n junctions and junction arrays can be assembled in over (2, 5)makes specific device fabrication large 95% yield with controllable electrical characteristics, and in addition, that these ly a random event and poses a serious issue junctions can be used to create integrated nanoscale field-effect transistor arrays for integration beyond the single-device el- with nanowires as both the conducting channel and gate electrode Nanowire ement level. A potential solution to the prob- junction arrays have been configured as key OR, AND, and NOR logic-gate struc tures with substantial gain and have been used to implement basic computation t of Chemistry and Chemical Biology, 2Di- f Engineering and Applied Sciences, Harvard Fundamental physical constraints and eco- top-down manufacturing during the next one d equally to this work. nomics are expected to limit continued min- to two decades(1, 2) and have thus motivated e should be addressed. e. iaturization in electronics by conventional efforts world wide to search for new strate- emag org SCIENCE VOL 294 9 NOVEMBER 2001 1313

in untreated cells. For degradation assays, cells were incubated at 25°C for 1 hour, and receptor number (total specific 125I-CYP binding sites) was determined after 24 hours of isoproterenol treatment and ex￾pressed as the percentage of receptor number as￾sessed in nonstimulated cells. Where necessary, MG132 (20 mM) or lactacystin (20 mM) mixed in serum-free media was added to cells 1 hour before stimulation. 16. P. van Kerkhof, R. Govers, C. M. Alves dos Santos, G. J. Strous, J. Biol. Chem. 275, 1575 (2000). 17. Flag epitope–tagged WT-b2AR and b2AR22, along with b-arrestin2, were transiently transfected in COS-7 cells with Lipofectamine. After agonist treat￾ment, receptors were immmunoprecipitated with Flag affinity beads, and the immunoprecipitates were resolved on SDS-PAGE and probed with antibodies Ub P4D1 and b2AR H-20. 18. W. P. Hausdorff et al., Proc. Natl. Acad. Sci. U.S.A. 88, 2979 (1991). 19. Confluent cells on 150-mm dishes were treated or not for 15 min with isoproterenol, after which cells were lysed in LB. Endogenous b2AR was immunopre￾cipitated with the antibody b2AR M-20. In the case of overexpressed b2AR, cells seeded at 400,000 per 100-mm dish were transfected with pcDNA3-Flag￾b2AR plasmid using Lipofectamine, and receptor was immunoprecipitated using FLAG affinity beads (Sig￾ma). Ubiquitinated species were detected with anti￾body Ub P4D1. 20. C. T. Chien, P. L. Bartel, R. Sternglanz, S. Fields, Proc. Natl. Acad. Sci. U.S.A. 88, 9578 (1991). 21. S. Fang, J. P. Jensen, R. L. Ludwig, K. H. Vousden, A. M. Weissman, J. Biol. Chem. 275, 8945 (2000). 22. R. Honda, H. Tanaka, H. Yasuda, FEBS Lett. 420, 25 (1997). 23. For coimmunoprecipitation of endogenous proteins from whole-brain extract, brain tissue was solubilized in LB (10). b-Arrestin was immunoprecipitated from extracts by incubation for 4 hours at 4°C with anti￾body specific for b-arrestin, covalently cross-linked to Reactigel beads (Pierce). Immunoprecipitated pro￾teins were analyzed by SDS-PAGE and detected by immunoblot analysis. For cellular experiments, COS-7 cells were transfected with COOH-terminal Flag-tagged b-arrestin and untagged Mdm2 plasmids. Flag–b-arrestins were immunoprecipitated with M2 Flag affinity beads (Sigma); the immunoprecipitates were separated by SDS-PAGE, and the presence of Mdm2 was demonstrated by immunoblotting with monoclonal antibodies (mAbs) 2A10 or AB1. 24. Supplementary Web material is available on Science Online at www.sciencemag.org/cgi/content/full/ 1063866/DC1. 25. T. Buschmann, S. Y. Fuchs, C.-G. Lee, Z-Q. Pan, Z. Ronai, Cell 101, 753 (2000). 26. Recombinant b2AR reconstituted in vesicles was used as the substrate in a ubiquitination reaction contain￾ing 20 mM Hepes (pH 7.5), 5 mM MgCl2, 2 mM dithiothreitol (DTT), 2 mM adenosine 59-triphos￾phate (ATP), 5 mg of ubiquitin, 20 mM MG132, and crude rabbit reticulocyte lysate (RRL, Promega), a source for the ubiquitination machinery (36) (5 ml/ reaction). The reactions were supplemented with ei￾ther His–b-arrestin2 (7 mg) or GST–b-arrestin2 (5 mg), GRK2, (1 mg), or Mdm2 [either GST-Mdm21-491 (8 mg) or COS-7 lysate with overexpressed Mdm2] where necessary. Reaction mixtures were incubated for 1 hour at 30°C. Ubiquitinated receptor (vesicles) was isolated by repeated washes with LB and centri￾fugation at 250,000g, 45 min. After addition of SDS– sample buffer, protein samples were incubated at 37°C for 2 hours before electrophoresis. 27. A cDNA construct of b-arrestin2 was cloned into pET-29a and was used to isolate recombinant SzTAG￾b-arrestin2His6 purified on S-protein agarose beads (Novagen), which was then used as the substrate in the b-arrestin2 in vitro ubiquitination reaction con￾taining 20 mM Hepes (pH 7.5), 5 mM MgCl2, 2 mM DTT, 2 mM ATP, 5 mg of ubiquitin, 20 mM MG132, and crude RRL, either supplemented or not with 100 mg of COS cell extract (clarified by centrifugation at 21,000g for 15 min) with or without overexpressed Mdm2. 28. K. Nakamura, M. F. Lazari, S. Li, C. Korgaonkar, M. Ascoli, Mol. Endocrinol. 13, 1295 (1999). 29. P. Tsao, T. Cao, M. von Zastrow, Trends Pharmacol. Sci. 22, 91 (2001) 30. Mdm2 truncation mutants were prepared by stan￾dard polymerase chain reaction protocols and sub￾cloned into pcDNA3. All sequences were confirmed with an automated ABI DNA sequencer (Howard Hughes Nucleic Acid Facility, Duke University). 31. J. Chen, V. Marechal, A. J. Levine, Mol. Cell. Biol. 13, 4107 (1993). 32. A. L. Parola, S. Lin, B. K. Kobilka, Anal. Biochem. 254, 88 (1997). 33. Flag epitope–tagged b2ARs expressed in HEK293 cells in six-well dishes were treated with or without iso￾proterenol for 30 min in serum-free medium at 37°C. Cell surface receptors were labeled with Flag mAb M1, and fluorescein isothiocyanate–conjugated goat antibody to mouse immunoglobulin G was used as secondary antibody. Receptor internalization was quantified as loss of cell surface receptors, as mea￾sured by flow cytometry. 34. O. B. Goodman Jr. et al., Nature 383, 447 (1996). 35. S. A. Laporte et al., Proc. Natl. Acad. Sci. U.S.A. 96, 3712 (1999). 36. S. Mori et al., Eur. J. Biochem. 247, 1190 (1997). 37. M. Bouvier et al., Mol. Pharmacol. 33, 133 (1988). 38. We thank D. Addison, M. Holben, and J. Turnbough for secretarial assistance; B. K. Kobilka for 0-Kb2AR plasmid; A. J. Levine for the Mdm2 plasmid and mAb 2A10; G. Lozano for providing the Mdm2-p53 null cell line; M. Delahunty for purified rb2AR; W. E. Miller for pAS2 constructs and advice in yeast experiments; F. T. Lin for pcDNA3-barrHis6 constructs; M. Cong for providing pcDNA3-b2AR22; S. J. Perry and K. L. Pierce for critical reading; H. E. Kendall and G. P. Irons for technical assistance; W. D. Capel for purified GRK2; and G. J. Sabo for assistance. Supported by NIH grant HL16037. R.J.L is an investigator of the Howard Hughes Medical Institute. 27 June 2001; accepted 17 September 2001 Published online 4 October 2001; 10.1126/science.1063866 Include this information when citing this paper. Logic Gates and Computation from Assembled Nanowire Building Blocks Yu Huang,1* Xiangfeng Duan,1* Yi Cui,1 Lincoln J. Lauhon,1 Kyoung-Ha Kim,2 Charles M. Lieber1,2† Miniaturization in electronics through improvements in established “top-down” fabrication techniques is approaching the point where fundamental issues are expected to limit the dramatic increases in computing seen over the past several decades. Here we report a “bottom-up” approach in which functional device el￾ements and element arrays have been assembled from solution through the use of electronically well-defined semiconductor nanowire building blocks. We show that crossed nanowire p-n junctions and junction arrays can be assembled in over 95% yield with controllable electrical characteristics, and in addition, that these junctions can be used to create integrated nanoscale field-effect transistor arrays with nanowires as both the conducting channel and gate electrode. Nanowire junction arrays have been configured as key OR, AND, and NOR logic-gate struc￾tures with substantial gain and have been used to implement basic computation. Fundamental physical constraints and eco￾nomics are expected to limit continued min￾iaturization in electronics by conventional top-down manufacturing during the next one to two decades (1, 2) and have thus motivated efforts world wide to search for new strate￾gies to meet expected computing demands of the future. Bottom-up approaches to nano￾electronics (2), where the functional electron￾ic structures are assembled from well-defined nanoscale building blocks, such as carbon nanotubes (3–8), molecules (9–11), and/or semiconductor nanowires (12–14), have the potential to go far beyond the limits of top￾down manufacturing. For example, single￾walled carbon nanotubes (NTs) have been used as building blocks to fabricate room￾temperature field-effect transistors (FETs) (3–5), diodes (6, 7) and recently, an inverter (8), which represents a key component for logic. However, the inability to control whether NTs are semiconducting or metallic (2, 5) makes specific device fabrication large￾ly a random event and poses a serious issue for integration beyond the single–device el￾ement level. A potential solution to the prob- 1 Department of Chemistry and Chemical Biology, 2 Di￾vision of Engineering and Applied Sciences, Harvard University, Cambridge, MA 02138, USA. *These authors contributed equally to this work. †To whom correspondence should be addressed. E￾mail: cml@cmliris.harvard.edu R ESEARCH A RTICLE www.sciencemag.org SCIENCE VOL 294 9 NOVEMBER 2001 1313 R EPORTS

REP。RTs lem of coexisting metallic and semiconduct- also to explore the assembly and properties of ing NTs involves selective destruction of me- integrated p-n junction arrays. Importantly, allic tubes (5), although such an approach electrical transport measurements made on a requires extensive top-down lithography and typical 4 by 1 crossed p-Si/n-Gan junction ubsequent processing to implement. array(Fig. 1B)show that the four nanoscale Semiconductor nanowires (NWs) have cross points form independently addressable also been used as building blocks for assem- p-n junctions with clear current rectification bling a range of nanodevices including FETs and similar turn-on voltages. These data dem- 12, 13), p-n diodes(13, 14), bipolar junction onstrate the high yield and reproducibility of transistors, and complementary inverters our crossed Nw p-n devices and represent ar 0 2 4 6 8 10(14). In contrast to NTs, these Nw devices important and necessary step for the rational can be assembled in a predictable manner ssembly of more complex devices such as 2000 because the electronic properties and sizes of logic gates(see below) the Nws can be precisely controlled during In addition to these low turn-on voltage 1500 synthesis(12-15) and methods exist for their diodes, high turn-on voltage p-n junctions parallel assembly (16). However, previous can be used as nanoscale FETs(Fig. 1 NW and NT single device elements represent Specifically, a p-channel FET with both a only an initial step toward nanoelectronic nanoscale conducting channel anda systems, which will require both the forma- nanoscale gate is formed from a n-GaN/p-si tion of device elements and integrated device crossed NW structure, we refer to these struc B arrays in high yield. To this end, we report tures as crossed NW FETs(cNW-FETs) The -2.0 2 4 gallium nitride(n-GaN) NWs to form crossed assemble cNW-FETs were reproducibly Bias (v) nanoscale p-n junctions and junction arrays in formed by increasing the oxide layer thick hich the electronic properties and function ness at the junctions by either thermal oxida- are controlled in a predictable manner to tion of the sinWs (18)or by passing a high provide both diode and FEt elements in high current through the junction in the air(20) M yield. Importantly, nanoscale p-n junction Transport data recorded on over 50 p-n junc. and FET arrays have been configured as Or, tions prepared in this way(Fig 1A) show that AND, and NOR logic gates with substantial turn-on voltages greater than 5 V can be gain, and these gates have been interconnect- achieved in nearly quantitative yield, while G O ed to demonstrate computation with a half- still maintaining good conduction through in adder. Our approach leads naturally through dividual NWs. The corresponding 1-v data 10 -0.5 0.0 0.5 0 the bottom-up paradigm to integration at the recorded on a typical CNW-FET, where the Bias (v nanoscale and represents a step toward the n-Gan NW is used as a nano-gate, exhibit a creation of sophisticated nanoelectronics. large decrease in conductance with increasing oltage distribution for crossed Nw used in this study were synthesized by nano- conductance can be changed by a factor of ange for low turn-on voltage jur cluster-catalyzed methods described previ- more than 105 with only a I-to 2-V variation ions formed from as-assembled Nw junctions, ously (14, 15, 17, 18)and had diameters of 10 in the nano-gate, whereas the conductance and the red cross-hatched area indicates high to 25 and 10 to 30 nm, respectively, although changes by only a factor of 10 when a global turn-on voltage devices after local oxidation of NWs as small as 2 nm can be prepared(15). back-gate is used(Fig. IC, top left inset).We the junction ( Top left inset)Histogram of turn- These NWs were chosen for our studies be- attribute the high sensitivity of the cNW on voltage for over 70 as-assembled junctions showing a narrow distribution around 1 V. The cause the oxide coating on their surfaces can FEts to the intrinsically thin gate dielectric high tion but generally fall into the range of 5 control of junction electronic properties. To plete understanding of this new type of FET to 10 V. (Top right inset)An example of an /-V demonstrate this feature, which is critical for will require further investigation. The repro- response for low (green) and high(red) turn-on assembly of more complex integrated devic- ducibility, large gate response, and potential age elements. the red curve is 000 for better viewing. The inset inside the es, we have assembled and characterized the for nanoscale integration make the cNW top right inset shows a typical scanning elec- electronic properties of a large number of FETs attractive for assembling more comple ron micrograph(SEM)of a crossed Nw device. crossed p-Si/n-GaN junctions(18)(Fig. 1). electronic devices in which FETs are critical Bar: 1 um.( B)l-v behavior for a 4(p) by 1(n) urrent-voltage (l-p) lements(22). In addition, these characteris- that the p-Si/n-Gan crossed nw devices tics contrast recent work on NTs(3-5, 8)that sent the -V h of the four hibit current rectification characteristic of p-n have used either global back gates, which are junctions and highlight reproducibility of as- diodes with a typical turn-on voltage of about incompatible with independent device fund a multiple crossed NW device. Bar: 2 um.(c) 1.o v(Fig. 1A)(9). These results are highly tion, or lithographically defined local gates, Gate-dependent I-V characteristics of a cros b- which use and are constrained by cor NW-FET. The Nw gate voltage for each I-v served in over 95% of the more than 70 al lithography to obtain nanoscale structures curve is indicated(o, 1, 2, and 3 V).(Top left crossed p-n Nw devices studied, and in ad- The high-yield assembly of crossed Nw inset)The red and blue curves show I versus dition, 85% of the devices exhibited low turn- p-n junctions and cNW-FETs enables the bot- for n-Nw( red)and global back (blue) on voltages between 0.6 and 1.3 V(Fig 1A, tom-up approach to be used for formation of top left inset). The reproducible assembly of more complex and functional electronic de when using the global back gate and crossed Nw structures with predictable elec- vices, such as logic gates. To demonstrate the respectively. Bottom right inset) The trical properties contrasts sharply with results flexibility of these nw device elements, we from NT-based devices and has enabled us have investigated both diode- and FET-based 1314 9NovembEr2001Vol294SciEncewww.sciencemag.org

lem of coexisting metallic and semiconduct￾ing NTs involves selective destruction of me￾tallic tubes (5), although such an approach requires extensive top-down lithography and subsequent processing to implement. Semiconductor nanowires (NWs) have also been used as building blocks for assem￾bling a range of nanodevices including FETs (12, 13), p-n diodes (13, 14), bipolar junction transistors, and complementary inverters (14). In contrast to NTs, these NW devices can be assembled in a predictable manner because the electronic properties and sizes of the NWs can be precisely controlled during synthesis (12–15) and methods exist for their parallel assembly (16). However, previous NW and NT single device elements represent only an initial step toward nanoelectronic systems, which will require both the forma￾tion of device elements and integrated device arrays in high yield. To this end, we report assembly of p-type silicon (p-Si) and n-type gallium nitride (n-GaN) NWs to form crossed nanoscale p-n junctions and junction arrays in which the electronic properties and function are controlled in a predictable manner to provide both diode and FET elements in high yield. Importantly, nanoscale p-n junction and FET arrays have been configured as OR, AND, and NOR logic gates with substantial gain, and these gates have been interconnect￾ed to demonstrate computation with a half￾adder. Our approach leads naturally through the bottom-up paradigm to integration at the nanoscale and represents a step toward the creation of sophisticated nanoelectronics. The single-crystal p-Si and n-GaN NWs used in this study were synthesized by nano￾cluster-catalyzed methods described previ￾ously (14, 15, 17, 18) and had diameters of 10 to 25 and 10 to 30 nm, respectively, although NWs as small as 2 nm can be prepared (15). These NWs were chosen for our studies be￾cause the oxide coating on their surfaces can be independently varied (18) to enable good control of junction electronic properties. To demonstrate this feature, which is critical for assembly of more complex integrated devic￾es, we have assembled and characterized the electronic properties of a large number of crossed p-Si/n-GaN junctions (18) (Fig. 1). Current-voltage (I-V) measurements show that the p-Si/n-GaN crossed NW devices ex￾hibit current rectification characteristic of p-n diodes with a typical turn-on voltage of about 1.0 V (Fig. 1A) (19). These results are highly reproducible: Current rectification was ob￾served in over 95% of the more than 70 crossed p-n NW devices studied, and in ad￾dition, 85% of the devices exhibited low turn￾on voltages between 0.6 and 1.3 V (Fig. 1A, top left inset). The reproducible assembly of crossed NW structures with predictable elec￾trical properties contrasts sharply with results from NT-based devices and has enabled us also to explore the assembly and properties of integrated p-n junction arrays. Importantly, electrical transport measurements made on a typical 4 by 1 crossed p-Si/n-GaN junction array (Fig. 1B) show that the four nanoscale cross points form independently addressable p-n junctions with clear current rectification and similar turn-on voltages. These data dem￾onstrate the high yield and reproducibility of our crossed NW p-n devices and represent an important and necessary step for the rational assembly of more complex devices such as logic gates (see below). In addition to these low turn-on voltage diodes, high turn-on voltage p-n junctions can be used as nanoscale FETs (Fig. 1C). Specifically, a p-channel FET with both a nanoscale conducting channel and a nanoscale gate is formed from a n-GaN/p-Si crossed NW structure; we refer to these struc￾tures as crossed NW FETs (cNW-FETs). The high turn-on voltage junctions required to assemble cNW-FETs were reproducibly formed by increasing the oxide layer thick￾ness at the junctions by either thermal oxida￾tion of the SiNWs (18) or by passing a high current through the junction in the air (20). Transport data recorded on over 50 p-n junc￾tions prepared in this way (Fig. 1A) show that turn-on voltages greater than 5 V can be achieved in nearly quantitative yield, while still maintaining good conduction through in￾dividual NWs. The corresponding I-V data recorded on a typical cNW-FET, where the n-GaN NW is used as a nano-gate, exhibit a large decrease in conductance with increasing gate voltage (Fig. 1C) (21). Specifically, the conductance can be changed by a factor of more than 105 with only a 1- to 2-V variation in the nano-gate, whereas the conductance changes by only a factor of 10 when a global back-gate is used (Fig. 1C, top left inset). We attribute the high sensitivity of the cNW￾FETs to the intrinsically thin gate dielectric between the crossed NWs, although a com￾plete understanding of this new type of FET will require further investigation. The repro￾ducibility, large gate response, and potential for nanoscale integration make the cNW￾FETs attractive for assembling more complex electronic devices in which FETs are critical elements (22). In addition, these characteris￾tics contrast recent work on NTs (3–5, 8) that have used either global back gates, which are incompatible with independent device func￾tion, or lithographically defined local gates, which use and are constrained by convention￾al lithography to obtain nanoscale structures. The high-yield assembly of crossed NW p-n junctions and cNW-FETs enables the bot￾tom-up approach to be used for formation of more complex and functional electronic de￾vices, such as logic gates. To demonstrate the flexibility of these NW device elements, we have investigated both diode- and FET-based Fig. 1. Crossed NW nanodevice elements. (A) Turn-on voltage distribution for crossed NW junctions. The green cross-hatched area indi￾cates the range for low turn-on voltage junc￾tions formed from as-assembled NW junctions, and the red cross-hatched area indicates high turn-on voltage devices after local oxidation of the junction. (Top left inset) Histogram of turn￾on voltage for over 70 as-assembled junctions showing a narrow distribution around 1 V. The high turn-on voltage devices have a broad dis￾tribution but generally fall into the range of 5 to 10 V. (Top right inset) An example of an I-V response for low (green) and high (red) turn-on voltage elements. The red curve is multiplied by 1000 for better viewing. The inset inside the top right inset shows a typical scanning elec￾tron micrograph (SEM) of a crossed NW device. Bar: 1 mm. (B) I-V behavior for a 4(p) by 1(n) multiple junction array. The four curves repre￾sent the I-V response for each of the four junctions and highlight reproducibility of as￾sembled device elements. (Inset) An example of a multiple crossed NW device. Bar: 2 mm. (C) Gate-dependent I-V characteristics of a crossed NW-FET. The NW gate voltage for each I-V curve is indicated (0, 1, 2, and 3 V ). ( Top left inset) The red and blue curves show I versus Vgate for n-NW (red) and global back (blue) gates when the bias is set at 1 V. The transcon￾ductance for this device was 80 and 280 nS (Vsd 5 1 V ) when using the global back gate and NW gate, respectively. (Bottom right inset) The measurement configuration. R EPORTS 1314 9 NOVEMBER 2001 VOL 294 SCIENCE www.sciencemag.org

REP。RTs logic(23). First, a two-input OR gate was series. In this way, the output depends on the cause it enables interconnection of arrays of realized by using a 2(p) by I(n) crossed p-n resistance ratio of the two cNW-FETs and the logic gates without signal restoration at each junction array with the two p-Si NWs as constant resistor. The logic 0 is observed stage(24). The truth table for this Nw device puts and the n-GaN NW as the output(Fig. when either one or both of the inputs is high (Fig 2D) summarizes the v-V, response and 2A). In this device, the output is low (logic 0)(Fig. 2H). In this case, the transistors are off demonstrates that the device behaves as a hen both input voltages are low(0 V), and and have resistances much higher than that of logic NOR gate. Lastly, our multiple-input the output is high (logic 1)when either or the constant resistor, and thus most of the logic NOR gates can function as Not gates both of the input voltages are high(5 V)(i ltage drops across the transistors. A logic 1 (simple inverters)by eliminating one of the 2B), where a high input corresponds to for- state can only be achieved when both of the inputs. ward bias of the corresponding p-n junction. transistors are on, i.e., when both inputs are The predictable assembly of logic OR, The output-input (o-V) voltage response low. The -V, relation(Fig. 2H, inset)shows AND, and NOR (NOT) gates enables the (Fig. 2B, inset) shows that V increases lin- constant low I, when the other input is high, organization of virtually any logic circuit and early with V when one input is set low(0 V), and a nonlinear response with large change in represents a substantial advance compared except for the region near 0 V. This low- V when the other input is set low. Analysis with previous studies of NTs and molecular response region is due to the finite turn-on of these data and those from similar struc- systems. First, the controllable electronic Itage of the p-n junctions and produces a tures demonstrates that these two-input NOr characteristics of the nw building blocks and logic output typically 0. 4 to 0.2 V less than gates routinely exhibit gains in excess of five, reproducible properties of the devices assem the input voltage. Small reductions in V do which is substantially larger than the gain bled from these blocks contrast with the not affect the operation of our logic gates reported for complementary inverters based much lower control achieved to date with because the low turn-on voltage contributions on Si-NWs(14) and carbon NTs(8). High NTs (3-8). We believe that predictable and are reproducible and can be readily accounted gain is a critical characteristic of gates be- reproducible assembly of device elements for in defining the o and 1 states. the v-p data also show a nearly constant high output when the second input is set high(5 V). The B01101C experimental truth table for the 1 by nw device(Fig. 1C)summarizes output response and confirms that device behaves as a logic OR gate. th sinw Vn(V) v(v) 0.0(0)501)4.8(1) note that assembly of more p-n junctions 501)00457(1) would produce a multiple input OR gate, i.e 012345 Silicon oxide 50)501)471 a I by n junction array for an n-input OR Address Level We have also fabricated an AND gate D E AND from a 1(p-si) by 3(n-GaN) multiple junction 11 (v)Y.(v) array(Fig. 2D). In this structure, the p-Si Nw is biased at 5 v: two of the gaN NWs are VMV V 000o0.71( used as inputs, and the third is used a gate 0.0050(1)0900 with a constant voltage to create a resistor by depleting a portion of the p-Si NW. The logic v. 01345 5.01)0.0(0)088(0 0 is observed from this device when either 50(1)5.01)1496(1 one or both of the inputs are low(Fig. 2E) AND Address Level because v =0 corresponds to a forward biased, low-resistance p-n junction that pull NOR down the output(logic"0). The logic I is n(v20)|v observed only when both inputs are high, E because this condition corresponds to re 0.0(0)0.00)4.85(1) 0.0(0)50(1)0.02(0) much larger than that of the constant resistor, 5.01)0.0(0)006(0 L.e., there is a small voltage drop across the constant resistor and a high voltage is Silicon oxide 011011 5.0)5.01)001(0) achieved at the output. The V-V data(Fig NOR Address Level 2E, inset)shows constant low v when the other input is low and nearly linear behavior crossed NW p-n junction (Insets) An example SEM(bar: 1 um) of the assembled"oR"gate and when the other input is set at high. The truth symbolic electronic circuit. ( B)The output voltage versus the four possible logic address level table for the nw device( Fig. 2F)summarizes inputs:(0,0); (0, 1): (10):(1,1), where logic 0 input is o V and logic 1 input is 5 V(same for the the input-output response and confirms that and v-v, when the other input is o ().(c) The experimental truth table for the or gate (D) bled by using a I(p-Si) by 3(n-GaN) cNW- voltage versus the four possible logic address level inputs (Inset)The V-V, where the ots) In addition, a logic NOR gate was assem- typical SEM(bar: 1 um)of the assembled aNd gate and symbolic electronic circuit.(E]The ou FET array(Fig. 2G). The NoR gate was dashed red(blue)lines correspond to Vo-Vi, and Vo-Vi2 when the other input is 0(1) le for fet to create a constant resistance of -100 1 by 3 crossed NW junction array(Insets) An example SEM(bar: 1 um) and symbolic electronic megohms, and the p-siNw channel was bi- id and dashed red(blue)lines correspond to V-V, and v-v when the othe ased at 5 V. The two remaining n-GaN NW of the data shows that device voltage gain is larger than 5.7 The measured nputs act as gates for two cNw-FETs in truth table for the NOR gate. www.sciencemagorgScieNceVol2949NovemBer2001 1315

logic (23). First, a two-input OR gate was realized by using a 2(p) by 1(n) crossed p-n junction array with the two p-Si NWs as inputs and the n-GaN NW as the output (Fig. 2A). In this device, the output is low (logic 0) when both input voltages are low (0 V), and the output is high (logic 1) when either or both of the input voltages are high (5 V) (Fig. 2B), where a high input corresponds to for￾ward bias of the corresponding p-n junction. The output-input (Vo-Vi ) voltage response (Fig. 2B, inset) shows that Vo increases lin￾early with Vi when one input is set low (0 V), except for the region near 0 V. This low￾response region is due to the finite turn-on voltage of the p-n junctions and produces a logic output typically 0.4 to 0.2 V less than the input voltage. Small reductions in Vo do not affect the operation of our logic gates because the low turn-on voltage contributions are reproducible and can be readily accounted for in defining the 0 and 1 states. The Vo-Vi data also show a nearly constant high output when the second input is set high (5 V). The experimental truth table for the 1 by 2 crossed NW device (Fig. 1C) summarizes the input￾output response and confirms that this NW device behaves as a logic OR gate. We also note that assembly of more p-n junctions would produce a multiple input OR gate, i.e., a 1 by n junction array for an n-input OR gate. We have also fabricated an AND gate from a 1(p-Si) by 3(n-GaN) multiple junction array (Fig. 2D). In this structure, the p-Si NW is biased at 5 V; two of the GaN NWs are used as inputs, and the third is used a gate with a constant voltage to create a resistor by depleting a portion of the p-Si NW. The logic 0 is observed from this device when either one or both of the inputs are low (Fig. 2E), because Vi 5 0 corresponds to a forward￾biased, low-resistance p-n junction that pulls down the output (logic “0”). The logic 1 is observed only when both inputs are high, because this condition corresponds to re￾verse-biased p-n diodes with resistances much larger than that of the constant resistor, i.e., there is a small voltage drop across the constant resistor and a high voltage is achieved at the output. The Vo-Vi data (Fig. 2E, inset) shows constant low Vo when the other input is low and nearly linear behavior when the other input is set at high. The truth table for the NW device (Fig. 2F) summarizes the input-output response and confirms that this device functions as a logic AND gate. In addition, a logic NOR gate was assem￾bled by using a 1(p-Si) by 3(n-GaN) cNW￾FET array (Fig. 2G). The NOR gate was configured with 2.5 V applied to one cNW￾FET to create a constant resistance of ;100 megohms, and the p-SiNW channel was bi￾ased at 5 V. The two remaining n-GaN NW inputs act as gates for two cNW-FETs in series. In this way, the output depends on the resistance ratio of the two cNW-FETs and the constant resistor. The logic 0 is observed when either one or both of the inputs is high (Fig. 2H). In this case, the transistors are off and have resistances much higher than that of the constant resistor, and thus most of the voltage drops across the transistors. A logic 1 state can only be achieved when both of the transistors are on, i.e., when both inputs are low. The Vo-Vi relation (Fig. 2H, inset) shows constant low Vo when the other input is high, and a nonlinear response with large change in Vo when the other input is set low. Analysis of these data and those from similar struc￾tures demonstrates that these two-input NOR gates routinely exhibit gains in excess of five, which is substantially larger than the gain reported for complementary inverters based on Si-NWs (14) and carbon NTs (8). High gain is a critical characteristic of gates be￾cause it enables interconnection of arrays of logic gates without signal restoration at each stage (24). The truth table for this NW device (Fig. 2I) summarizes the Vo-Vi response and demonstrates that the device behaves as a logic NOR gate. Lastly, our multiple-input logic NOR gates can function as NOT gates (simple inverters) by eliminating one of the inputs. The predictable assembly of logic OR, AND, and NOR (NOT) gates enables the organization of virtually any logic circuit and represents a substantial advance compared with previous studies of NTs and molecular systems. First, the controllable electronic characteristics of the NW building blocks and reproducible properties of the devices assem￾bled from these blocks contrast with the much lower control achieved to date with NTs (3–8). We believe that predictable and reproducible assembly of device elements Fig. 2. Nanowire nano-logic gates. (A) Schematics of logic OR gate constructed from a 2 by 1 crossed NW p-n junction. (Insets) An example SEM (bar: 1 mm) of the assembled “OR” gate and symbolic electronic circuit. (B) The output voltage versus the four possible logic address level inputs: (0,0); (0,1); (1,0); (1,1), where logic 0 input is 0 V and logic 1 input is 5 V (same for the below). (Inset) The output-input (Vo-Vi ) relation. The solid and dashed red (blue) lines show Vo-Vi1 and Vo-Vi2 when the other input is 0 (1). (C) The experimental truth table for the OR gate. (D) Schematic of logic AND gate constructed from a 1 by 3 crossed NW junction array. (Insets) A typical SEM (bar: 1 mm) of the assembled AND gate and symbolic electronic circuit. (E) The output voltage versus the four possible logic address level inputs. (Inset) The Vo-Vi , where the solid and dashed red (blue) lines correspond to Vo-Vi1 and Vo-Vi2 when the other input is 0 (1). (F) The experimental truth table for the AND gate. (G) Schematic of logic NOR gate constructed from a 1 by 3 crossed NW junction array. (Insets) An example SEM (bar: 1 mm) and symbolic electronic circuit. (H) The output voltage versus the four possible logic address level inputs. (Inset) The Vo-Vi relation, where the solid and dashed red (blue) lines correspond to Vo-Vi1 and Vo-Vi2 when the other input is 0 (1). The slope of the data shows that device voltage gain is larger than 5. (I) The measured truth table for the NOR gate. R EPORTS www.sciencemag.org SCIENCE VOL 294 9 NOVEMBER 2001 1315

REP。RTs and arrays is especially important for integra- gates and a low-gain diode and gate is due veloping much greater tication in tion without resorting to extensive top-down to the high gain of the cNW-FET NOR gates. sembly and further material lithography to connect to those nT devices We believe that further improvements in de- synthesis that function. Second, the use of crossed Nw vice performance could be obtained by using devices and arrays leads naturally to integra- cNW-FET elements for all of the logic ele ferences an tion at the nanoscale and should be contrasted ments(24). Importantly, the data summa. 1.R. Compano, L Molenkamp, D. ). Paul, Technolog with NT (3-5, 8) and molecular (9-11)de- rized in the experimental truth table(Fig. 3F) viceswheretheelementsizesreportedtodemonstratethattheresponseisthatoftheMicroelectronicsAdvancedResearchInitiativehttp:// date (length for NTs and area for molecules) binary logic SUM operation, and thus that we have been determined by the same top-down have implemented a basic computation with 3. s ) Tans, R. M Verschueren, C.Dekker, Nature 393 lithography used in conventional electronics. the Nw logic devices Overall, we believe that our predictable 4. R MartelL, T. Schmidt, H.R. Shea. T Hertel. Ph. AND and NOR gates to implement basic and reproducible bench-top assembl 5. P. G. Collins, M. S. Arnold, Ph. Avouris, Science 292, mputation in the form of an XOR gate( Fig. nanoscale crossed p-n diode and cNW-FET function SUM, and a half adder(Fig. 3B), demonstration of all critical logic gates and 1. ws tg(19g/ stma, L a 3A), which corresponds to the binary logic elements and arrays, which have enabled the 6.Z hich corresponds to the addition of two basic computation, represents an important 8. V. Derycke, R binary bits. The XOR gate is configured by step toward integrated nanoelectronics built Nano Letters 1, 453(2001)(Web release, 26 August using the output from AND and NOR gates from primarily bottom-up versus top-down 9. C. P. Collier et al, Science 285, 391(1999 as the input to a second NOR gate, whereas approaches. Further improvements can be 10. C P Collier et al. Science 289, 1172(2000) defined metal electrode arrays(25)and by 12 your, Appl. Phys. Lett. 286, 1550(2001) ice,1.M. he logic half adder uses an additional logic made by assembling NWs directly onto pre 11. M. A Reed, J. n, A M. Rawlett, D AND gate as the CARRY. The truth table the proposed logic XOR is summarized in creating more highly integrated circuit ele Cui, X. Duan, J. Hu, C M. Lieber, J. Phys. Chem. B 04,5213[2000 Fig. 3C. Importantly, the experimental a- ments by feeding the output from NW toN..Nature 409 66 (2001). cu, wang and E) show(i)that the output is logic state 0 nate the conventional lithography used to 15. Y. Cui, L) Lauhon, M.S. Gudiksen,].Wang, CM or low when the inputs are both low or high, wire-up devices in this study. In addition, in a Lieber, Appl. Phys. Lett. 78, 2214(2001) and logic state I or high when one input is crossbar array with 5-nm diameter NWs, it 16. Y Huang. XDuan, QWei,CMLieber, Science 291 low and the other is high; and (ii) that the would be possible to achieve device densities 17. x Duan, C M. Lieber. /Am.Chem.Soc.122.188 esponse is highly nonlinear. The linear re- approaching 10/cm2, which is off the (2000) ponse region corresponds to a voltage gain present semiconductor road map for tor 18. Single-crystal p-type Si-NWs were grown of more than five and is typical of the devices down manufacturing. To achieve this goal of dopant(SiH :B He 100 00:1to60001)(15).ing measured to date. This large gain achieved in bottom-up manufacturing in the future will rystal GaN-NWs were prepared by a laser-assist an XOR configured from CNW-FET NOR require substantial work-for example, in de- n:GaN: Fe=95: 5)(17)and Logic XOR Logie half adder emoved by HF etching(14 or increased in thick- ANDH CARRY to a second XOR SUM (B) Vil vi2 Vil Vi2 dder.()Truth table Si-NWs were aligned on the Si/SiO, surface fron for logic XOR gate.(D NOR AND XOR nel, and crossed GaN-NWs were deposited by us- The solid and dashed d(blue) lines sh to NOR defined by electron Au)to the nanowires were hen the other inpur urements made on individual p-Si and n- the v-v. data 0 behavior. The p-Si NWs have tv es of 0.5 to 10 megohms and were determined by the E F growth. The n-GaN NWs have two-terminal resis- D、oey2 The turn-on voltages of crossed Nw p-n re increased by joule he 0.00)0.00)0.82(0)0.020) e ou 0.0(0)50(1)1080)41(1) 00 11 5.01)0.00)0.95(0)4.78(1) four possible logic ad- turn-on voltage. The red line in the top rig 501)5.01)4.981)0.010 the Xor g XOR Address level perimental truth table r the logic half adder. The logic half adder was obtained by using the XOr gate as the SUM and 21. The cNw-FET on/off ratio can vary from 10 to 105 an AND gate as the CARrY depending on the p-Si Nw carrier concentration. In 1316 9NovembEr2001Vol294SciEncewww.sciencemag.org

and arrays is especially important for integra￾tion without resorting to extensive top-down lithography to connect to those NT devices that function. Second, the use of crossed NW devices and arrays leads naturally to integra￾tion at the nanoscale and should be contrasted with NT (3–5, 8) and molecular (9–11) de￾vices, where the element sizes reported to date (length for NTs and area for molecules) have been determined by the same top-down lithography used in conventional electronics. Lastly, we have interconnected multiple AND and NOR gates to implement basic computation in the form of an XOR gate (Fig. 3A), which corresponds to the binary logic function SUM, and a half adder (Fig. 3B), which corresponds to the addition of two binary bits. The XOR gate is configured by using the output from AND and NOR gates as the input to a second NOR gate, whereas the logic half adder uses an additional logic AND gate as the CARRY. The truth table for the proposed logic XOR is summarized in Fig. 3C. Importantly, the experimental Vo-Vi transport data for the XOR device (Fig. 3, D and E) show (i) that the output is logic state 0 or low when the inputs are both low or high, and logic state 1 or high when one input is low and the other is high; and (ii) that the response is highly nonlinear. The linear re￾sponse region corresponds to a voltage gain of more than five and is typical of the devices measured to date. This large gain achieved in an XOR configured from CNW-FET NOR gates and a low-gain diode AND gate is due to the high gain of the cNW-FET NOR gates. We believe that further improvements in de￾vice performance could be obtained by using cNW-FET elements for all of the logic ele￾ments (24). Importantly, the data summa￾rized in the experimental truth table (Fig. 3F) demonstrate that the response is that of the binary logic SUM operation, and thus that we have implemented a basic computation with the NW logic devices. Overall, we believe that our predictable and reproducible bench-top assembly of nanoscale crossed p-n diode and cNW-FET elements and arrays, which have enabled the demonstration of all critical logic gates and basic computation, represents an important step toward integrated nanoelectronics built from primarily bottom-up versus top-down approaches. Further improvements can be made by assembling NWs directly onto pre￾defined metal electrode arrays (25) and by creating more highly integrated circuit ele￾ments by feeding the output from NW to NW. Implementing these approaches could elimi￾nate the conventional lithography used to wire-up devices in this study. In addition, in a crossbar array with 5-nm diameter NWs, it would be possible to achieve device densities approaching 1012/cm2 , which is off the present semiconductor road map for top￾down manufacturing. To achieve this goal of bottom-up manufacturing in the future will require substantial work—for example, in de￾veloping much greater sophistication in as￾sembly and further improving materials synthesis. References and Notes 1. R. Compano, L. Molenkamp, D. J. Paul, Technology Roadmap for Nanoelectronics, European Commission IST Programme: Future and Emerging Technologies, Microelectronics Advanced Research Initiative; http:// nanoworld.org/NanoLibrary/nanoroad.pdf. 2. C. M. Lieber, Sci. Am. (September 2001), p. 58. 3. S. J. Tans, R. M. Verschueren, C. Dekker, Nature 393, 49 (1998). 4. R. Martel, T. Schmidt, H. R. Shea, T. Hertel, Ph. Avouris, Appl. Phys. Lett. 73, 2447 (1998). 5. P. G. Collins, M. S. Arnold, Ph. Avouris, Science 292, 706 (2001). 6. Z. Yao, H. W. C. Postma, L. Balents, C. Dekker, Nature 402, 273 (1999). 7. M. S. Fuhrer et al., Science 288, 494 (2000). 8. V. Derycke, R. Martel, J. Appenzeller, Ph. Avouris, Nano Letters 1, 453 (2001) ( Web release, 26 August 2001). 9. C. P. Collier et al., Science 285, 391 (1999). 10. C. P. Collier et al., Science 289, 1172 (2000). 11. M. A. Reed, J. Chen, A. M. Rawlett, D. W. Price, J. M. Tour, Appl. Phys. Lett. 286, 1550 (2001). 12. Y. Cui, X. Duan, J. Hu, C. M. Lieber, J. Phys. Chem. B 104, 5213 (2000). 13. X. Duan, Y. Huang, Y. Cui, J. Wang, C. M. Lieber, Nature 409, 66 (2001). 14. Y. Cui, C. M. Lieber, Science 291, 851 (2001). 15. Y. Cui, L. J. Lauhon, M. S. Gudiksen, J. Wang, C. M. Lieber, Appl. Phys. Lett. 78, 2214 (2001). 16. Y. Huang, X. Duan, Q. Wei, C. M. Lieber, Science 291, 630 (2001). 17. X. Duan, C. M. Lieber, J. Am. Chem. Soc. 122, 188 (2000). 18. Single-crystal p-type Si-NWs were grown by using Au nanocluster catalysts, SiH4 reactant, and B2H6 dopant (SiH4:B2H6, 1000:1 to 6000:1) (15). Single￾crystal GaN-NWs were prepared by a laser-assist￾ed catalytic growth with iron as the catalyst (tar￾get composition: GaN:Fe 5 95:5) (17) and are naturally n-type due to nitrogen vacancies or ox￾ygen impurities (26). The SiNW surfaces consist of a ;1-nm-thick amorphous oxide, which can be removed by HF etching (14) or increased in thick￾ness by thermal oxidation before device assembly. The GaN-NWs have only a monolayer-thick oxide over-layer (27), making them ideal for forming crossed NW junctions. Stable solutions of Si-NWs and GaN-NWs were prepared by sonication in ethanol for 5 to 10 s. Individual and multiple crossed NW junctions were prepared by using a layer-by-layer fluidic alignment strategy (16): First, Si-NWs were aligned on the Si/SiO2 surface from the ethanol solution by using a microfluidic chan￾nel, and crossed GaN-NWs were deposited by us￾ing the microfluidic channel oriented perpendicular to the original SiNW flow. Au/Ti electrical contacts (50 nm Ti; 70 nm Au) to the nanowires were defined by electron-beam lithography and elec￾tron-beam evaporation. 19. I-V measurements made on individual p-Si and n￾GaN NWs in crossed NW devices show linear I-V behavior. The p-Si NWs have two-terminal resistanc￾es of 0.5 to 10 megohms and were determined by the SiH4:B2H6 ratio (1000:1 to 6000:1) used during growth. The n-GaN NWs have two-terminal resis￾tances of 50 to 500 kilohms. 20. The turn-on voltages of crossed NW p-n junctions were increased by Joule heating the junctions in air. Because the crossing point dominates the junction resistance (13, 14), a high current will locally heat the crossing point and increase the oxide layer between crossed NWs, and thereby the junction resistance/ turn-on voltage. The red line in the top right inset of Fig. 1A shows the large change in turn-on voltage after passing a 10-mA current through the junction for about 4 min; the resistance changes of the indi￾vidual NWs changed less than about 10%. 21. The cNW-FET on/off ratio can vary from 103 to 105, depending on the p-Si NW carrier concentration. In Fig. 3. Nanowire com￾putation. (A) Sche￾matic of logic XOR gate constructed with the output from an AND and a NOR as the input to a second NOR gate. (B) Sche￾matic for logic half adder. (C) Truth table for logic XOR gate. (D) XOR output voltage versus input voltages. The solid and dashed red (blue) lines show Vo-Vi1 and Vo-Vi2 when the other input is 0 (1). The slope of the Vo-Vi data shows that the gain exceeds 10. The XOR gate was achieved by connect￾ing the output elec￾trodes of an AND and NOR gate to two in￾puts of another NOR gate. (E) The output voltage versus the four possible logic ad￾dress level inputs for the XOR gate. (F) Ex￾perimental truth table for the logic half adder. The logic half adder was obtained by using the XOR gate as the SUM and an AND gate as the CARRY. R EPORTS 1316 9 NOVEMBER 2001 VOL 294 SCIENCE www.sciencemag.org

REP。RTs neral, p-Si NWs grown with a higher dopant ratio 24. The OR and ANd gates were assembled by using p-n 26. J. L Pankov, T. Nitride(GaN)/ (SiH: B2 H6 =1000: 1) have lower resistance and junctions( diode logic) and do not exhibit voltage gain owever, they would show gain if imple lowe er on/off ratios of -10 to 105. In addition, from 30 to 20 and ground connections to the p-Si Nw. The AND 28. We thank H Park for helpful discussion CM.L 22. S. M. Sze, Semiconductor Devices, Physics and Tech- llel (versus series for OR). In addition, we note iley. New York. 1985), pp. 208-210 n-channel transistors are possible and Research Agency W. Hill, The Art of Electronics(Cam ould enable reduced power dissipat S. Y Huang, X Duan &C M. Lieber, unpublished results. Logic Circuits with Carbon ter of about I nm and that are situated on top of the al gate wires. Their coordinates are regis- Nanotube transistors tered with respect to alignment markers. Finally ontact electrodes and interconnect wires ar fabricated with electron-beam lithography by Adrian Bachtold, Peter Hadley, Takeshi Nakanishi, Cees Dekker evaporating Au directly on the nanotube without an adhesion layer. We demonstrate logic circuits with field-effect transistors based on single Very strong doping of the nanotube channel carbon nanotubes. Our device layout features local gates that provide excellent can be achieved with this layout(Fig. 2A)(20) apacitive coupling between the gate and nanotube enabling strong electro- Starting from a negative gate voltage the static doping of the nanotube from p-doping to n-doping and the study of the current first decreases. then becomes immea- nonconventional long-range screening of charge along the one-dimensional drably small, and finally increases again. Thi anotubes. the transistors show favorable device characteristics such as higl indicates that y shifts the fermi level succes- gain(10), a large on-off ratio(10), and room-temperature operation. sively from the valence band(accumulation re Importantly, the local-gate layout allows for integration of multiple devices on gime) to the gap(depletion), and finally to the a single chip. Indeed, we demonstrate one, two-, and three-transistor circuits conduction band (inversion) of the semicon- that exhibit a range of digital logic operations, such as an inverter, a logic NOR ducting nanotube. The nearby Al gate thus a static random-access memory cell, and an ac ring oscillator makes it possible to change the doping of the nanotube over the full range from the pto the The anticipated limits to the further miniatur- oxidized Si wafer(6, 7, 9), the tip of an atomic n-doped regime ization of microelectronics have led to in- force microscope(10-12), a second nanotube Our nanotube transistors can be class tense research directed toward the dev (3), an ionic solution(14), or a capping al enhancement-mode p-type FETs(21),because a ment of molecular electronics (1). The use of film(15). The layouts of these devices do not strong modulation of the current through the gle-wall carbon nanotubes has stimulated allow integration of multiply connected devices notube FET is possible when a small negativ these efforts, because these molecules exhibit (16). For example, the most popular nanotube- gate voltage is applied. The current versus bias a range of suitable properties for nanoelec- transistor layout uses a backgate, which applies voltage d characteristics(Fig 3)are typical fo tronics. Various basic single-nanotube com- the same gate voltage to all transistors on the FETs(22). From the data in Figs. 2 and 3, we ponents have recently been demonstrated hip. In contrast, our gate consists of a micro- can extract a transconductance of our nanotube such as molecular wires, diodes, field-effect fabricated Al wire with a well-insulating native transistors of 0.3 us and a lower limit of the transistors, and single-electron transistors(2- AL,O3 layer(17), which lies beneath a semi- on/off ratio of at least 105. The maximum cur- 8). The next challenge in the development of conducting nanotube that is electrically contact rent at which the nanotube transistor can operate molecular electronics is to go beyond single- ed to two Au electrodes(Fig. 1, A and B). In is on the order of 100 nA and the on-resistance olecule components and integrate such de. this configuration, the Al, O, thickness of a few is 26 megaohms for d=-1.3 V and K=-1.3 vices onto a chip to demonstrate digital logic nanometers is much shorter than the separation V. perations. Here, we report such logic cir- between the contact electrodes(-100 nm), en- For any further development of op cuits composed of single- nanotube field-ef- abling an excellent capacitive coupling between logic circuits, a gain(1) at large bias fect transistors. In addition to the realization the gate and the nanotube. Moreover, different is a crucial requirement, because the output of of logic circuits, our new device layout also local Al gates can easily be patterned such that one logic structure must be able to drive the enables substantial electrostatic doping for each one addresses a different nanotube transis- input of the next logic structure. The output modest gate voltages, which allows us to tor. This layout thus allows the integration of typically has to provide a voltage swing of udy the nonconventional screening of multiple nanotube field-effect transistors about 1 V. Figure 3 indicates that in our tran- charge along the one-dimensional nanotubes. (FETs)on the same chip(Fig. IC) sistors, a change in the output by more than 1 V Our nanotube transistors have a local gate Our nanotube circuits are realized in a three- occurs when the input voltage is changed by 0.1 that is insulated from the nanotube by a gate step process. First, Al gates are patterned using V. This indicates a large-signal gain >10. A oxide layer of only a few nanometers thickness. electron beam lithography (18)on an oxidized large gain combined with a large output In previous circuits, the gate consisted of an Si wafer. The insulating layer consists of the swing can be obtained because the gate is so native oxide that grows by exposing the sample close to the nanotube. Our technique allows to air. The precise thickness of this layer is for a much larger gain than has been achieved Department of Applied Physics, Delft University of Tech- difficult to determine but is on the order of a with thick gate oxides or planar gates used in w nanometers Second, single-wall car- previous nanotube FETs(6, 7. 9, 23). Gre Condense Ecole normale he de la ma- bon nanotubes produced by laser ablation are A major point of our report is that small lomond. 75005 Paris France. dispersed on the wafer from a dichloroethane circuits combining our nanotube transistors can tTo whom correspondence should be addressed. E- suspension. With an atomic force microscope, be used for a variety of logic elements. Here, we mail dekker@mb. tn tudelft nl those nanotubes are selected that have a diame describe our demonstration of an inverter. a emag org SCIENCE VOL 294 9 NOVEMBER 2001 1317

general, p-Si NWs grown with a higher dopant ratio (SiH4:B2H6 5 1000:1) have lower resistance and smaller on/off ratios of ;103; those synthesized with a lower dopant ratio (6000:1) have higher resistance and larger on/off ratios of ;104 to 105. In addition, the carrier mobility typically varies from 30 to 200 cm2/V-s, depending on doping. 22. S. M. Sze, Semiconductor Devices, Physics and Tech￾nology ( Wiley, New York, 1985), pp. 208–210. 23. P. Horowitz, W. Hill, The Art of Electronics (Cam￾bridge Univ. Press, Cambridge, 1989). 24. The OR and AND gates were assembled by using p-n junctions (diode logic) and do not exhibit voltage gain; however, they would show gain if implemented by using cNW-FETs. For example, logic OR can be imple￾mented with the NOR gate by reversing the 5-V bias and ground connections to the p-Si NW. The AND function could also be implemented by using cNW-FETs in parallel (versus series for OR). In addition, we note that both p- and n-channel transistors are possible and would enable reduced power dissipation. 25. Y. Huang, X. Duan & C. M. Lieber, unpublished results. 26. J. I. Pankov, T. D. Moustakas, Gallium Nitride (GaN) I (Academic Press, San Diego, 1998), pp. 259–265. 27. N. J. Watkins, G. W. Wicks, Yongli Gao, Appl. Phys. Lett. 75, 2602 (1999). 28. We thank H. Park for helpful discussion. C.M.L. ac￾knowledges support of this work by the Office of Naval Research and the Defense Advanced Projects Research Agency. 12 September 2001; accepted 16 October 2001 Logic Circuits with Carbon Nanotube Transistors Adrian Bachtold,* Peter Hadley, Takeshi Nakanishi, Cees Dekker† We demonstrate logic circuits with field-effect transistors based on single carbon nanotubes. Our device layout features local gates that provide excellent capacitive coupling between the gate and nanotube, enabling strong electro￾static doping of the nanotube from p-doping to n-doping and the study of the nonconventional long-range screening of charge along the one-dimensional nanotubes. The transistors show favorable device characteristics such as high gain (.10), a large on-off ratio (.105 ), and room-temperature operation. Importantly, the local-gate layout allows for integration of multiple devices on a single chip. Indeed, we demonstrate one-, two-, and three-transistor circuits that exhibit a range of digital logic operations, such as an inverter, a logic NOR, a static random-access memory cell, and an ac ring oscillator. The anticipated limits to the further miniatur￾ization of microelectronics have led to in￾tense research directed toward the develop￾ment of molecular electronics (1). The use of single-wall carbon nanotubes has stimulated these efforts, because these molecules exhibit a range of suitable properties for nanoelec￾tronics. Various basic single-nanotube com￾ponents have recently been demonstrated, such as molecular wires, diodes, field-effect transistors, and single-electron transistors (2– 8). The next challenge in the development of molecular electronics is to go beyond single￾molecule components and integrate such de￾vices onto a chip to demonstrate digital logic operations. Here, we report such logic cir￾cuits composed of single-nanotube field-ef￾fect transistors. In addition to the realization of logic circuits, our new device layout also enables substantial electrostatic doping for modest gate voltages, which allows us to study the nonconventional screening of charge along the one-dimensional nanotubes. Our nanotube transistors have a local gate that is insulated from the nanotube by a gate oxide layer of only a few nanometers thickness. In previous circuits, the gate consisted of an oxidized Si wafer (6, 7, 9), the tip of an atomic force microscope (10–12), a second nanotube (13), an ionic solution (14), or a capping Al film (15). The layouts of these devices do not allow integration of multiply connected devices (16). For example, the most popular nanotube￾transistor layout uses a backgate, which applies the same gate voltage to all transistors on the chip. In contrast, our gate consists of a micro￾fabricated Al wire with a well-insulating native Al2O3 layer (17), which lies beneath a semi￾conducting nanotube that is electrically contact￾ed to two Au electrodes (Fig. 1, A and B). In this configuration, the Al2O3 thickness of a few nanometers is much shorter than the separation between the contact electrodes (;100 nm), en￾abling an excellent capacitive coupling between the gate and the nanotube. Moreover, different local Al gates can easily be patterned such that each one addresses a different nanotube transis￾tor. This layout thus allows the integration of multiple nanotube field-effect transistors (FETs) on the same chip (Fig. 1C). Our nanotube circuits are realized in a three￾step process. First, Al gates are patterned using electron beam lithography (18) on an oxidized Si wafer. The insulating layer consists of the native oxide that grows by exposing the sample to air. The precise thickness of this layer is difficult to determine, but is on the order of a few nanometers (19). Second, single-wall car￾bon nanotubes produced by laser ablation are dispersed on the wafer from a dichloroethane suspension. With an atomic force microscope, those nanotubes are selected that have a diame￾ter of about 1 nm and that are situated on top of the Al gate wires. Their coordinates are regis￾tered with respect to alignment markers. Finally, contact electrodes and interconnect wires are fabricated with electron-beam lithography by evaporating Au directly on the nanotube without an adhesion layer. Very strong doping of the nanotube channel can be achieved with this layout (Fig. 2A) (20). Starting from a negative gate voltage Vg, the current I first decreases, then becomes immea￾surably small, and finally increases again. This indicates that Vg shifts the Fermi level succes￾sively from the valence band (accumulation re￾gime) to the gap (depletion), and finally to the conduction band (inversion) of the semicon￾ducting nanotube. The nearby Al gate thus makes it possible to change the doping of the nanotube over the full range from the p- to the n-doped regime. Our nanotube transistors can be classified as enhancement-mode p-type FETs (21), because a strong modulation of the current through the nanotube FET is possible when a small negative gate voltage is applied. The current versus bias voltage Vsd characteristics (Fig. 3) are typical for FETs (22). From the data in Figs. 2 and 3, we can extract a transconductance of our nanotube transistors of 0.3 mS and a lower limit of the on/off ratio of at least 105 . The maximum cur￾rent at which the nanotube transistor can operate is on the order of 100 nA and the on-resistance is 26 megaohms for Vsd 5 –1.3 V and Vg 5 –1.3 V. For any further development of operational logic circuits, a gain (.1) at large bias voltage is a crucial requirement, because the output of one logic structure must be able to drive the input of the next logic structure. The output typically has to provide a voltage swing of about 1 V. Figure 3 indicates that in our tran￾sistors, a change in the output by more than 1 V occurs when the input voltage is changed by 0.1 V. This indicates a large-signal gain .10. A large gain combined with a large output swing can be obtained because the gate is so close to the nanotube. Our technique allows for a much larger gain than has been achieved with thick gate oxides or planar gates used in previous nanotube FETs (6, 7, 9, 23). A major point of our report is that small circuits combining our nanotube transistors can be used for a variety of logic elements. Here, we describe our demonstration of an inverter, a Department of Applied Physics, Delft University of Tech￾nology, Lorentzweg 1, 2628 CJ Delft, Netherlands. *Present address: Laboratoire de Physique de la Ma￾tie`re Condense´e, E´cole Normale Superieure, 24 Rue Lhomond, 75005 Paris, France. †To whom correspondence should be addressed. E￾mail: dekker@mb.tn.tudelft.nl R EPORTS www.sciencemag.org SCIENCE VOL 294 9 NOVEMBER 2001 1317