PM0056Slife.augmentedProgramming manualSTM32F10xxx/20xxx/21xxx/L1xxxxCortex-M3 programming manualIntroductionThis programming manual provides information for application and system-level softwaredevelopers.ItgivesafulldescriptionoftheSTM32F10xxx/20xxx/21xxx/L1xxxxCortex-M3processorprogrammingmodel,instructionsetandcoreperipheralsTheSTM32F10xxx/20xxx/21xxx/L1xxxxCortex-M3processorisahighperformance32-bitprocessordesignedforthemicrocontrollermarket.Itoffers significantbenefitstodevelopers, including:Outstanding processing performancecombinedwitha fast interrupt handling·5.Enhanced system debugwithextensivebreakpointandtracecapabilitiesEfficientprocessorcore,systemandmemoriesUitra-low-powerconsumptionwithintegratedsleepmodes.Platformsecurity1/156December2017DocID15491Rev6www.st.com
December 2017 DocID15491 Rev 6 1/156 1 PM0056 Programming manual STM32F10xxx/20xxx/21xxx/L1xxxx Cortex®-M3 programming manual Introduction This programming manual provides information for application and system-level software developers. It gives a full description of the STM32F10xxx/20xxx/21xxx/L1xxxx Cortex®-M3 processor programming model, instruction set and core peripherals. The STM32F10xxx/20xxx/21xxx/L1xxxx Cortex®-M3 processor is a high performance 32-bit processor designed for the microcontroller market. It offers significant benefits to developers, including: • Outstanding processing performance combined with a fast interrupt handling • Enhanced system debug with extensive breakpoint and trace capabilities • Efficient processor core, system and memories • Ultra-low-power consumption with integrated sleep modes • Platform security www.st.com
PM0056ContentsContents1About this document101.110Typographicalconventions1.210Listofabbreviationsforregisters1.310AbouttheSTM32Cortex-M3processorandcoreperipherals.111.3.1System level interface121.3.2Integratedconfigurabledebug1.3.3Cortex-M3 processor features and benefits summary..121.3.4Cortex-M3 core peripherals.122The Cortex-M3 processor132.113Programmers model2.1.1.13Processormode and privilege levelsfor software execution2.1.2..13Stacks2.1.3..14Coreregisters2.1.4Exceptionsand interrupts.222.1.5Datatypes.222.1.6The Cortex microcontroller software interface standard (CMSiS) ....232.2Memory model.242.2.1Memory regions, types and attributes.252.2.2Memorysystemorderingofmemoryaccesses.252.2.3.26Behavior ofmemoryaccesses2.2.4.26Softwareorderingofmemoryaccesses2.2.5.27Bit-banding2.2.6..29Memoryendianness2.2.7..30Synchronization primitives2.2.8.31Programminghintsforthesynchronizationprimitives2.3·32Exceptionmodel2.3.1..32Exceptionstates2.3.2.32Exceptiontypes2.3.3Exception handlers.342.3.4Vectortable..352.3.5.35Exception priorities2.3.6.36Interruptprioritygrouping2.3.7Exception entry and return.37A2/156DocID15491Rev6
Contents PM0056 2/156 DocID15491 Rev 6 Contents 1 About this document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.1 Typographical conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2 List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3 About the STM32 Cortex®-M3 processor and core peripherals . . . . . . . . 10 1.3.1 System level interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.3.2 Integrated configurable debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.3.3 Cortex®-M3 processor features and benefits summary . . . . . . . . . . . . . 12 1.3.4 Cortex®-M3 core peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 The Cortex®-M3 processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 Programmers model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.1 Processor mode and privilege levels for software execution . . . . . . . . . 13 2.1.2 Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.3 Core registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1.4 Exceptions and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.1.5 Data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.1.6 The Cortex® microcontroller software interface standard (CMSIS) . . . . 23 2.2 Memory model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.2.1 Memory regions, types and attributes . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.2.2 Memory system ordering of memory accesses . . . . . . . . . . . . . . . . . . . 25 2.2.3 Behavior of memory accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.2.4 Software ordering of memory accesses . . . . . . . . . . . . . . . . . . . . . . . . 26 2.2.5 Bit-banding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.2.6 Memory endianness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2.7 Synchronization primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.2.8 Programming hints for the synchronization primitives . . . . . . . . . . . . . . 31 2.3 Exception model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.3.1 Exception states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.3.2 Exception types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.3.3 Exception handlers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.3.4 Vector table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.3.5 Exception priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.3.6 Interrupt priority grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.3.7 Exception entry and return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
PM0056Contents2.4Fault handling392.4.1.39Faulttypes2.4.2...40Fault escalation and hard faults2.4.3Fault status registers and fault address registers.412.4.4.41Lockup.2.541Power management2.5.1Enteringsleepmode..422.5.2.42Wakeupfromsleepmode2.5.3.43Theexternal event input2.5.4Power management programming hints.433The Cortex-M3 instruction set443.144Instructionsetsummary3.249Intrinsic functions3.350About the instruction descriptions3.3.1.50Operands3.3.2.51RestrictionswhenusingPCorSP3.3.3..51Flexible second operand3.3.4.52Shift operations3.3.5.55Addressalignment3.3.6.56PC-relativeexpressions3.3.7Conditional execution.563.3.8.58Instructionwidthselection3.4Memory access instructions593.4.1..60ADR3.4.2LDRandSTR,immediateoffset.613.4.3.63LDRandSTR,registeroffset3.4.4..64LDR and STR, unprivileged3.4.5..65LDR, PC-relative3.4.6LDMandSTM...673.4.7..68PUSHandPOP3.4.8LDREX and STREX.703.4.9CLREX.713.572General data processing instructions3.5.1ADD,ADC,SUB,SBC,andRSB.733.5.2AND,ORR,EOR,BIC,andORN.75A3/156DocID15491Rev6
DocID15491 Rev 6 3/156 PM0056 Contents 6 2.4 Fault handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.4.1 Fault types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.4.2 Fault escalation and hard faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.4.3 Fault status registers and fault address registers . . . . . . . . . . . . . . . . . 41 2.4.4 Lockup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.5 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.5.1 Entering sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.5.2 Wakeup from sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.5.3 The external event input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.5.4 Power management programming hints . . . . . . . . . . . . . . . . . . . . . . . . 43 3 The Cortex®-M3 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.1 Instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.2 Intrinsic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.3 About the instruction descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.3.1 Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.3.2 Restrictions when using PC or SP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.3.3 Flexible second operand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.3.4 Shift operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.3.5 Address alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.3.6 PC-relative expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.3.7 Conditional execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.3.8 Instruction width selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.4 Memory access instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.4.1 ADR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.4.2 LDR and STR, immediate offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.4.3 LDR and STR, register offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.4.4 LDR and STR, unprivileged . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.4.5 LDR, PC-relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.4.6 LDM and STM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.4.7 PUSH and POP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.4.8 LDREX and STREX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 3.4.9 CLREX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 3.5 General data processing instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.5.1 ADD, ADC, SUB, SBC, and RSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.5.2 AND, ORR, EOR, BIC, and ORN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
PM0056Contents763.5.3ASR,LSL, LSR, ROR,and RRX3.5.4CLZ773.5.5CMPandCMN...783.5.6MOV and MVN.793.5.7MOVT.803.5.8.81REV, REV16, REVSH, and RBIT3.5.9.82TSTandTEQ3.683Multiply and divide instructions3.6.1...83MUL, MLA, and MLS3.6.2UMULL, UMLAL, SMULL,and SMLAL.853.6.3SDIVandUDIV.863.7 87Saturating instructions3.7.1SSAT and USAT.873.8Bitfield instructions883.8.1.89BFC and BFI3.8.2SBFX and UBFX..893.8.3.90SXT and UXT3.8.4.91Branch and control instructions3.8.5B, BL, BX, and BLX..923.8.6CBZand CBNZ..933.8.7IT.943.8.8.96TBB and TBH3.997Miscellaneous instructions3.9.1BKPT..983.9.2CPS..983.9.3DMB.993.9.4DSB.1003.9.5ISB ..1003.9.6MRS1003.9.7MSR1013.9.8NOP.1023.9.9SEV.1023.9.10SVC1033.9.11WFE.1033.9.12WFI1044105Core peripheralsA4/156DocID15491Rev6
Contents PM0056 4/156 DocID15491 Rev 6 3.5.3 ASR, LSL, LSR, ROR, and RRX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 3.5.4 CLZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.5.5 CMP and CMN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 3.5.6 MOV and MVN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 3.5.7 MOVT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 3.5.8 REV, REV16, REVSH, and RBIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 3.5.9 TST and TEQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 3.6 Multiply and divide instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 3.6.1 MUL, MLA, and MLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 3.6.2 UMULL, UMLAL, SMULL, and SMLAL . . . . . . . . . . . . . . . . . . . . . . . . . 85 3.6.3 SDIV and UDIV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 3.7 Saturating instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 3.7.1 SSAT and USAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 3.8 Bitfield instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.8.1 BFC and BFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 3.8.2 SBFX and UBFX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 3.8.3 SXT and UXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 3.8.4 Branch and control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 3.8.5 B, BL, BX, and BLX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 3.8.6 CBZ and CBNZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 3.8.7 IT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 3.8.8 TBB and TBH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 3.9 Miscellaneous instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 3.9.1 BKPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 3.9.2 CPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 3.9.3 DMB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 3.9.4 DSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 3.9.5 ISB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 3.9.6 MRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 3.9.7 MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 3.9.8 NOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 3.9.9 SEV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 3.9.10 SVC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 3.9.11 WFE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 3.9.12 WFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 4 Core peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
PM0056Contents4.1105AbouttheSTM32coreperipherals4.2105Memory protection unit (MPU)4.2.1MPUaccesspermissionattributes..1064.2.2.108MPUmismatch4.2.3.108Updating an MPU region1104.2.4MPU design hints and tips4.2.5111MPU typeregister (MPU_TYPER)4.2.6.112MPUcontrolregister(MPUCR)4.2.7..113MPU region number register (MPU_RNR)4.2.8114MPUregion baseaddress register (MPU_RBAR)4.2.9.116MPUregion attribute and size register (MPU_RASR)4.3...118Nested vectored interrupt controller (NVIC)4.3.1The CMSIS mapping of the Cortex-M3NVIC registers.1194.3.2.120Interruptset-enablereqisters(NVICISERx).4.3.3..121Interrupt clear-enable registers (NVIC_ICERx).1224.3.4Interrupt set-pending registers (NVIC_ISPRx)4.3.5.123Interrupt clear-pending registers (NVIC_ICPRx)4.3.6.124Interruptactivebitregisters(NVICIABRx)4.3.7125Interrupt priority registers (NVIC_IPRx)4.3.8..126Software trigger interrupt register (NVIC_STIR)4.3.9126Level-sensitiveandpulseinterrupts..1274.3.10NVIC designhintsandtips.1284.3.11NVICregistermap4.4.129System control block (SCB)4.4.1..129Auxiliarycontrolregister (SCB_ACTLR)4.4.2.130CPUIDbaseregister(SCB_CPUID)4.4.3Interrupt control and state register (SCB_ICSR)1314.4.4.133Vectortableoffsetregister(SCB_VTOR)4.4.5Application interrupt and reset control register (SCB_AIRCR).....1344.4.6.136Systemcontrol register(SCB_SCR)4.4.7.137Configuration and control register (SCB_CCR)4.4.8..138System handler priority registers (SHPRx)4.4.9.140Systemhandlercontrolandstateregister(SCB_SHCSR)4.4.10..142Configurablefaultstatusregister(SCBCFSR)4.4.11Hard fault status register (SCB_HFSR).1454.4.12Memory management fault address register (SCB_MMFAR)..1474.4.13Bus fault address register (SCB_BFAR).147A5/156DocID15491Rev6
DocID15491 Rev 6 5/156 PM0056 Contents 6 4.1 About the STM32 core peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 4.2 Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 4.2.1 MPU access permission attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 4.2.2 MPU mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 4.2.3 Updating an MPU region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 4.2.4 MPU design hints and tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 4.2.5 MPU type register (MPU_TYPER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 4.2.6 MPU control register (MPU_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 4.2.7 MPU region number register (MPU_RNR) . . . . . . . . . . . . . . . . . . . . . 113 4.2.8 MPU region base address register (MPU_RBAR) . . . . . . . . . . . . . . . . 114 4.2.9 MPU region attribute and size register (MPU_RASR) . . . . . . . . . . . . . 116 4.3 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . .118 4.3.1 The CMSIS mapping of the Cortex®-M3 NVIC registers . . . . . . . . . . . 119 4.3.2 Interrupt set-enable registers (NVIC_ISERx) . . . . . . . . . . . . . . . . . . . . 120 4.3.3 Interrupt clear-enable registers (NVIC_ICERx) . . . . . . . . . . . . . . . . . . 121 4.3.4 Interrupt set-pending registers (NVIC_ISPRx) . . . . . . . . . . . . . . . . . . . 122 4.3.5 Interrupt clear-pending registers (NVIC_ICPRx) . . . . . . . . . . . . . . . . . 123 4.3.6 Interrupt active bit registers (NVIC_IABRx) . . . . . . . . . . . . . . . . . . . . . 124 4.3.7 Interrupt priority registers (NVIC_IPRx) . . . . . . . . . . . . . . . . . . . . . . . . 125 4.3.8 Software trigger interrupt register (NVIC_STIR) . . . . . . . . . . . . . . . . . 126 4.3.9 Level-sensitive and pulse interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 126 4.3.10 NVIC design hints and tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 4.3.11 NVIC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 4.4 System control block (SCB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 4.4.1 Auxiliary control register (SCB_ACTLR) . . . . . . . . . . . . . . . . . . . . . . . 129 4.4.2 CPUID base register (SCB_CPUID) . . . . . . . . . . . . . . . . . . . . . . . . . . 130 4.4.3 Interrupt control and state register (SCB_ICSR) . . . . . . . . . . . . . . . . . 131 4.4.4 Vector table offset register (SCB_VTOR) . . . . . . . . . . . . . . . . . . . . . . 133 4.4.5 Application interrupt and reset control register (SCB_AIRCR) . . . . . . 134 4.4.6 System control register (SCB_SCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 136 4.4.7 Configuration and control register (SCB_CCR) . . . . . . . . . . . . . . . . . . 137 4.4.8 System handler priority registers (SHPRx) . . . . . . . . . . . . . . . . . . . . . 138 4.4.9 System handler control and state register (SCB_SHCSR) . . . . . . . . . 140 4.4.10 Configurable fault status register (SCB_CFSR) . . . . . . . . . . . . . . . . . 142 4.4.11 Hard fault status register (SCB_HFSR) . . . . . . . . . . . . . . . . . . . . . . . . 145 4.4.12 Memory management fault address register (SCB_MMFAR) . . . . . . . 147 4.4.13 Bus fault address register (SCB_BFAR) . . . . . . . . . . . . . . . . . . . . . . . 147
ContentsPM00564.4.14..148Systemcontrolblockdesignhintsandtips4.4.15SCBregistermap1484.5.150SysTick timer (STK)4.5.1.151SysTickcontrolandstatusregister(STK_CTRL)4.5.2...152SysTickreloadvalueregister(STK_LOAD)4.5.3SysTick current value register (STK_VAL)..1534.5.4SysTick calibration value register (STK_CALIB).1534.5.5154SysTickdesignhints andtips.4.5.6154SysTickregistermap5155RevisionhistoryA6/156DocID15491Rev6
Contents PM0056 6/156 DocID15491 Rev 6 4.4.14 System control block design hints and tips . . . . . . . . . . . . . . . . . . . . . 148 4.4.15 SCB register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 4.5 SysTick timer (STK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 4.5.1 SysTick control and status register (STK_CTRL) . . . . . . . . . . . . . . . . 151 4.5.2 SysTick reload value register (STK_LOAD) . . . . . . . . . . . . . . . . . . . . . 152 4.5.3 SysTick current value register (STK_VAL) . . . . . . . . . . . . . . . . . . . . . . 153 4.5.4 SysTick calibration value register (STK_CALIB) . . . . . . . . . . . . . . . . . 153 4.5.5 SysTick design hints and tips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 4.5.6 SysTick register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
PM0056ListoftablesList of tablesTable 1..14Summaryofprocessormode,executionprivilegelevel,andstackuseoptions..15Table 2.Coreregistersetsummary.16Table 3.PSRregistercombinations..17Table 4.APSRbit definitionsTable 5..18IPSRbitdefinitions...19Table 6.EPSRbitdefinitions.20Table 7.PRIMASKregisterbitdefinitions.20Table 8.FAULTMASKregisterbitdefinitions...21Table 9.BASEPRIregisterbitassignments...Table 10.22CONTROLregisterbitdefinitions25Table 11.Ordering ofmemoryaccesses.26Table12.Memoryaccessbehavior.28Table 13.SRAMmemorybit-banding regions.28Table 14.Peripheral memorybit-banding regions31Table 15.Ccompilerintrinsicfunctionsforexclusiveaccessinstructions..33Table 16.Propertiesofthedifferentexceptiontypes.39Table 17.Exceptionreturnbehavior..Table 18.Faults.40++.41Table 19.FaultstatusandfaultaddressregistersTable 20.44Cortex-M3 instructions....49Table 21.CMSiSintrinsicfunctionstogeneratesomeCortex-M3instructionsTable 22.50CMSiS intrinsicfunctionstoaccess the specialregisters...57Table 23.Conditioncodesuffixes....Table 24..59MemoryaccessinstructionsTable 25.62Immediate,pre-indexedandpost-indexedoffsetrangesTable 26..66label-PCoffsetranges...72Table 27.Dataprocessinginstructions..Table 28.Multiply and divide instructions...83.88Table 29.PackingandunpackinginstructionsTable 30...91Branchandcontrol instructions..Table 31..92BranchrangesTable 32...97Miscellaneous instructions.105Table 33.STM32coreperipheralregisterregionsTable 34..106Memoryattributessummary...107Table 35.TEX, C, B, and S encoding....107Table 36.Cache policyformemory attribute encoding108Table 37.AP encoding....Table 38.111MemoryregionattributesforSTM32117Table 39.ExampleSiZEfieldvalues..Table 40..117MPUregistermapandresetvalues.119Table 41.Mapping of interrupts to the interrupt variablesTable 42.IPRbitassignments..125.127Table 43.CMSISfunctionsforNVICcontrolTable 44.128NVICregistermapandresetvalues..135Table 45.Priority grouping .Table 46.138SystemfaulthandlerpriorityfieldsTable 47..148SCBregistermapandresetvalueforSTM32F2andSTM32LTable 48.SCB register map and reset values..149A7/156DocID15491Rev6
DocID15491 Rev 6 7/156 PM0056 List of tables 8 List of tables Table 1. Summary of processor mode, execution privilege level, and stack use options. . . . . . . . . 14 Table 2. Core register set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 3. PSR register combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 4. APSR bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 5. IPSR bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 6. EPSR bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 7. PRIMASK register bit definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 8. FAULTMASK register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 9. BASEPRI register bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 10. CONTROL register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 11. Ordering of memory accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 12. Memory access behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 13. SRAM memory bit-banding regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 14. Peripheral memory bit-banding regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 15. C compiler intrinsic functions for exclusive access instructions . . . . . . . . . . . . . . . . . . . . . 31 Table 16. Properties of the different exception types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 17. Exception return behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 18. Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 19. Fault status and fault address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 20. Cortex-M3 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 21. CMSIS intrinsic functions to generate some Cortex-M3 instructions . . . . . . . . . . . . . . . . . 49 Table 22. CMSIS intrinsic functions to access the special registers. . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 23. Condition code suffixes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 24. Memory access instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 25. Immediate, pre-indexed and post-indexed offset ranges . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 26. label-PC offset ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 27. Data processing instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 28. Multiply and divide instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 29. Packing and unpacking instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 30. Branch and control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 31. Branch ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table 32. Miscellaneous instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Table 33. STM32 core peripheral register regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 34. Memory attributes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table 35. TEX, C, B, and S encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table 36. Cache policy for memory attribute encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table 37. AP encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 38. Memory region attributes for STM32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Table 39. Example SIZE field values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Table 40. MPU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Table 41. Mapping of interrupts to the interrupt variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 42. IPR bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Table 43. CMSIS functions for NVIC control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Table 44. NVIC register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Table 45. Priority grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Table 46. System fault handler priority fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Table 47. SCB register map and reset value for STM32F2 and STM32L . . . . . . . . . . . . . . . . . . . . 148 Table 48. SCB register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
ListoftablesPM0056Table 49.....154SysTickregistermap and resetvalues.....................155Table 50.Documentrevisionhistory..S8/156DocID15491Rev6
List of tables PM0056 8/156 DocID15491 Rev 6 Table 49. SysTick register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Table 50. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
PM0056List offiguresList of figuresFigure 1..11STM32Cortex-M3implementation..14Figure 2.Processorcoreregisters.....16Figure3.APSR, IPSR and EPSR bit assignments.16Figure 4.PSRbitassignments.............20Figure 5.PRIMASKbitassignmentsFigure 6.....20FAULTMASKbitassignments.21Figure 7.BASEPRIbitassignments21Figure 8.CONTROLbitassignments..24Figure 9.Memorymap....29Figure 10.Bit-bandmapping.30Figure 11.Little-endian example.35Figure 12.VectortableFigure 13.ASR#3.53LSR#3..53Figure 14.Figure 15.LSL#3.54Figure 16.ROR#3....5455Figure17.RRX #3110Figure 18.Subregionexample..Figure 19.NVIC_iPRxregistermapping125Figure 20.142CFSRsubregistersA9/156DocID15491Rev6
DocID15491 Rev 6 9/156 PM0056 List of figures 9 List of figures Figure 1. STM32 Cortex-M3 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 2. Processor core registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 3. APSR, IPSR and EPSR bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 4. PSR bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 5. PRIMASK bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 6. FAULTMASK bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 7. BASEPRI bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 8. CONTROL bit assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 9. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 10. Bit-band mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 11. Little-endian example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 12. Vector table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 13. ASR#3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 14. LSR#3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 15. LSL#3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 16. ROR #3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 17. RRX #3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 18. Subregion example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Figure 19. NVIC_IPRx register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Figure 20. CFSR subregisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
AboutthisdocumentPM00561AboutthisdocumentThisdocumentprovidestheinformationrequiredforapplicationandsystem-level softwaredevelopment.Itdoesnotprovideinformationondebugcomponents,features,oroperation.This material is formicrocontroller softwareand hardware engineers,including thosewhohavenoexperienceofArmproducts.arm1.1TypographicalconventionsThetypographicalconventionsusedinthisdocumentare:italicHighlightsimportantnotes,introduces specialterminology.denotesinternalcross-references,andcitationsEnclosereplaceabletermsforassemblersyntaxwheretheyappearincodeorcodefragments.Forexample:LDRSB,[,#]1.2ListofabbreviationsforregistersThe following abbreviations are used in register descriptions:read/write (rw)Software can read and write to these bits.read-only (r)Softwarecanonlyreadthesebitswrite-only (w)Software can only write to this bit. Reading the bit returns the resetvalue.read/clear(rc_w1)Softwarecanreadaswell asclearthisbitbywriting1.Writing'O'hasno effect on thebit value.read/clear (rc_wo)Softwarecan read as well as clearthis bit bywriting 0.Writing1'hasnoeffectonthebitvaluetoggle (t)Software can onlytoggle this bit by writing'1.Writingo'has no effect.Reserved (Res.)Reservedbit,mustbekeptatresetvalue.1.3About the STM32 Cortex-M3 processor and coreperipheralsTheCortex-M3processorisbuiltonahigh-performanceprocessorcore,witha3-stagepipelineHarvard architecture,making it idealfor demanding embeddedapplications.Theprocessordeliversexceptional powerefficiencythroughanefficientinstructionsetandextensively optimized design,providing high-end processinghardware including single-cycle32x32multiplicationanddedicatedhardwaredivision.A10/156DocID15491Rev6
About this document PM0056 10/156 DocID15491 Rev 6 1 About this document This document provides the information required for application and system-level software development. It does not provide information on debug components, features, or operation. This material is for microcontroller software and hardware engineers, including those who have no experience of Arm products. 1.1 Typographical conventions The typographical conventions used in this document are: 1.2 List of abbreviations for registers The following abbreviations are used in register descriptions: 1.3 About the STM32 Cortex®-M3 processor and core peripherals The Cortex-M3 processor is built on a high-performance processor core, with a 3-stage pipeline Harvard architecture, making it ideal for demanding embedded applications. The processor delivers exceptional power efficiency through an efficient instruction set and extensively optimized design, providing high-end processing hardware including singlecycle 32x32 multiplication and dedicated hardware division. italic Highlights important notes, introduces special terminology, denotes internal cross-references, and citations. Enclose replaceable terms for assembler syntax where they appear in code or code fragments. For example: LDRSB , [, #] read/write (rw) Software can read and write to these bits. read-only (r) Software can only read these bits. write-only (w) Software can only write to this bit. Reading the bit returns the reset value. read/clear (rc_w1) Software can read as well as clear this bit by writing 1. Writing ‘0’ has no effect on the bit value. read/clear (rc_w0) Software can read as well as clear this bit by writing 0. Writing ‘1’ has no effect on the bit value. toggle (t) Software can only toggle this bit by writing ‘1’. Writing ‘0’ has no effect. Reserved (Res.) Reserved bit, must be kept at reset value