STM32F103xCSTM32F103xDSTSTM32F103xEHigh-densityperformancelineARM-based32-bitMCUwith256to512KBFlash,USB,CAN,11timers,3ADCs,13communicationinterfacesFeatures■■Core:ARM32-bitCortexTM-M3CPUWLCSP6472MHzmaximumfrequencyLQFP6410×10mmLFBGA100 10×10mmLQFP10014×14mm,LFBGA14410×10mm1.25DMIPS/MHz (Dhrystone2.1)LQFP14420×20mmperformance at owait statememoryUpto112fast/Oportsaccess51/80/112I/Os,allmappableon16Single-cyclemultiplicationandhardwareexternalinterruptvectors andalmostalldivision5V-tolerantMemoriesUpto11timers256to512KbytesofFlashmemoryUp to four 16-bit timers, each with up to 4upto64KbytesofSRAMIC/OC/PwMorpulsecounterandFlexiblestaticmemorycontroller with4quadrature(incremental)encoderinputChipSelect.Supports Compact Flash,2×16-bit motor control PWM timerswithSRAM,PSRAM,NORandNANDmemoriesdead-time generation and emergency stopLCDparallelinterface,8080/6800modes2 ×watchdog timers (Independentand Clock,reset and supplymanagementWindow)2.0to3.6Vapplicationsupplyand/OsSysTick timer:a24-bitdowncounter-POR,PDR,andprogrammablevoltage2×16-bitbasictimerstodrivetheDACdetector (PVD)Upto13communicationinterfaces4-to-16MHz crystaloscillatorUp to2×/Pc interfaces (SMBus/PMBus)Internal8MHzfactory-trimmedRC-Upto5USARTs(ISO7816interface,LINInternal4okHzRCwithcalibrationIrDAcapability,modemcontrol)Upto3SPls (18Mbit/s),2with12s32kHzoscillatorforRTCwithcalibrationinterfacemultiplexedLowpowerCANinterface(2.0BActive)Sleep,StopandStandbymodes-USB2.0full speedinterfaceVBAT supplyforRTC and backup registersSDIOinterface3×12-bit, 1μsA/D converters (upto21CRC calculation unit,96-bit unique IDchannels)■ECOPACk? packagesConversion range:0 to3.6VTriple-sampleandholdcapabilityTable1.Device summaryTemperature sensorReferencePartnumber2×12-bitD/AconvertersDMA:12-channelDMAcontrollerSTM32F103RCSTM32F103VCSTM32F103xCSTM32F103ZCSupportedperipherals:timers,ADCs,DAC,SDIO,Ss,SPls,2CsandUSARTsSTM32F103RDSTM32F103VDSTM32F103xDSTM32F103ZDDebugmodeSTM32F103RESTM32F103ZESerial wire debug (SWD)& JTAG interfacesSTM32F103xESTM32F103VECortex-M3EmbeddedTraceMacrocellTMSeptember2009Doc ID14611Rev71/123www.st.com
September 2009 Doc ID 14611 Rev 7 1/123 1 STM32F103xC STM32F103xD STM32F103xE High-density performance line ARM-based 32-bit MCU with 256 to 512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces Features ■ Core: ARM 32-bit Cortex™-M3 CPU – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division ■ Memories – 256 to 512 Kbytes of Flash memory – up to 64 Kbytes of SRAM – Flexible static memory controller with 4 Chip Select. Supports Compact Flash, SRAM, PSRAM, NOR and NAND memories – LCD parallel interface, 8080/6800 modes ■ Clock, reset and supply management – 2.0 to 3.6 V application supply and I/Os – POR, PDR, and programmable voltage detector (PVD) – 4-to-16 MHz crystal oscillator – Internal 8 MHz factory-trimmed RC – Internal 40 kHz RC with calibration – 32 kHz oscillator for RTC with calibration ■ Low power – Sleep, Stop and Standby modes – VBAT supply for RTC and backup registers ■ 3 × 12-bit, 1 µs A/D converters (up to 21 channels) – Conversion range: 0 to 3.6 V – Triple-sample and hold capability – Temperature sensor ■ 2 × 12-bit D/A converters ■ DMA: 12-channel DMA controller – Supported peripherals: timers, ADCs, DAC, SDIO, I2Ss, SPIs, I2Cs and USARTs ■ Debug mode – Serial wire debug (SWD) & JTAG interfaces – Cortex-M3 Embedded Trace Macrocell™ ■ Up to 112 fast I/O ports – 51/80/112 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant ■ Up to 11 timers – Up to four 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input – 2 × 16-bit motor control PWM timers with dead-time generation and emergency stop – 2 × watchdog timers (Independent and Window) – SysTick timer: a 24-bit downcounter – 2 × 16-bit basic timers to drive the DAC ■ Up to 13 communication interfaces – Up to 2 × I2C interfaces (SMBus/PMBus) – Up to 5 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) – Up to 3 SPIs (18 Mbit/s), 2 with I2S interface multiplexed – CAN interface (2.0B Active) – USB 2.0 full speed interface – SDIO interface ■ CRC calculation unit, 96-bit unique ID ■ ECOPACK® packages Table 1. Device summary Reference Part number STM32F103xC STM32F103RC STM32F103VC STM32F103ZC STM32F103xD STM32F103RD STM32F103VD STM32F103ZD STM32F103xE STM32F103RE STM32F103ZE STM32F103VE FBGA LQFP64 10 × 10 mm, LQFP100 14 × 14 mm, LQFP144 20 × 20 mm LFBGA100 10 × 10 mm LFBGA144 10 × 10 mm WLCSP64 www.st.com
ContentsSTM32F103xC,STM32F103xD,STM32F103xEContents1Introduction92Description102.1Device overview112.214Full compatibility throughout the family2.315Overview2.3.1ARM?CortexTM-M3corewithembeddedFlashandSRAM.152.3.2.15EmbeddedFlashmemory2.3.3.15CRC (cyclicredundancycheck)calculationunit2.3.4..15EmbeddedSRAM2.3.5FSMC(flexiblestaticmemorycontroller).152.3.6LCDparallel interface.162.3.7.16Nestedvectored interruptcontroller(NVIC)2.3.8.16External interrupt/event controller (EXTI)2.3.9.16Clocksandstartup2.3.10Bootmodes.172.3.11Powersupplyschemes172.3.12Power supply supervisor172.3.13.17Voltage regulator2.3.14Low-powermodes.182.3.15DMA :.182.3.16.18RTC (real-timeclock)and backup registers2.3.17.19Timers andwatchdogs2.3.182cbus..202.3.19Universalsynchronous/asynchronousreceivertransmitters(USARTs)212.3.20Serial peripheral interface (SPI).212.3.21.21Inter-integrated sound (2s)2.3.22SDIO.21.212.3.23Controllerareanetwork (CAN)2.3.24.22Universal serialbus(USB)2.3.25GPIOs (general-purpose inputs/outputs).222.3.26ADC (analog to digital converter)222.3.27DAC (digital-to-analog converter).22.232.3.28TemperaturesensorS2/123Doc ID14611Rev7
Contents STM32F103xC, STM32F103xD, STM32F103xE 2/123 Doc ID 14611 Rev 7 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.1 ARM® Cortex™-M3 core with embedded Flash and SRAM . . . . . . . . . 15 2.3.2 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.3 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 15 2.3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.5 FSMC (flexible static memory controller) . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.6 LCD parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.7 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 16 2.3.8 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.9 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.10 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.11 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.12 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.13 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.14 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.15 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.16 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 18 2.3.17 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.18 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.19 Universal synchronous/asynchronous receiver transmitters (USARTs) 21 2.3.20 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.21 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.22 SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.23 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.24 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.25 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.26 ADC (analog to digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.27 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.28 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
STM32F103xC,STM32F103xD,STM32F103xEContents.232.3.29SerialwireJTAGdebugport(SWJ-DP)2.3.30EmbeddedTraceMacrocellT.23324Pinoutsandpindescriptions4.38Memorymapping5.39Electrical characteristics5.1:39Parameterconditions5.1.1.39Minimumandmaximumvalues5.1.2.39Typical values5.1.3..39Typical curves5.1.4Loading capacitor.395.1.5Pin input voltage..395.1.6Powersupplyscheme.405.1.7.40Current consumption measurement5.2Absolutemaximum ratings415.3.: 42Operating conditions5.3.1..42Generaloperatingconditions5.3.2..43Operatingconditionsatpower-up/power-down5.3.3Embeddedresetandpowercontrolblockcharacteristics..435.3.4.44Embedded reference voltage5.3.5.44Supply current characteristics5.3.6..54Externalclocksourcecharacteristics5.3.7Internalclocksourcecharacteristics.585.3.8PLLcharacteristics.605.3.9Memory characteristics..605.3.10FSMCcharacteristics.615.3.11EMCcharacteristics..805.3.12.81Absolute maximum ratings (electrical sensitivity)5.3.13.82/Oportcharacteristics5.3.14NRSTpincharacteristics.865.3.15..87TIMtimercharacteristics5.3.16Communicationsinterfaces.885.3.17CAN (controllerarea network) interface.975.3.1812-bitADCcharacteristics.985.3.19DACelectrical specifications103S3/123Doc ID14611Rev 7
STM32F103xC, STM32F103xD, STM32F103xE Contents Doc ID 14611 Rev 7 3/123 2.3.29 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3.30 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3 Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 43 5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 43 5.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5.3.10 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.3.12 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 81 5.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.3.15 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 5.3.16 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.3.17 CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.3.18 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.3.19 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
ContentsSTM32F103xC,STM32F103xD,STM32F103xE5.3.20105Temperaturesensorcharacteristics6Packagecharacteristics1066.1Packagemechanicaldata1066.2Thermal characteristics1146.2.1Referencedocument1146.2.2Selecting the product temperature range...115.7Part numbering1178Revision history118S4/123Doc ID14611Rev7
Contents STM32F103xC, STM32F103xD, STM32F103xE 4/123 Doc ID 14611 Rev 7 5.3.20 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 6.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 6.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.2.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 115 7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
STM32F103xC,STM32F103xD,STM32F103xEList oftablesList of tablesTable 1.Device summary...................Table 2.STM32F103xC,STM32F103xD and STM32F103xEfeatures and peripheral counts....11Table 3.STM32F103xxfamily.......14.19Table 4.High-densitytimerfeaturecomparisonTable 5..30High-densitySTM32F103xxpindefinitionsTable 6.....36FSMCpindefinitionTable 7..41Voltagecharacteristics41Table 8.Currentcharacteristics...42Table 9.Thermalcharacteristics.....42Table 10.General operatingconditions.43Table 11.Operatingconditionsatpower-up/power-down.43Table 12.Embeddedresetandpowercontrolblockcharacteristics.Table 13....44Embeddedinternal referencevoltage........Table 14.MaximumcurrentconsumptioninRunmode,codewithdataprocessing.45running from Flash....Table 15.Maximum currentconsumption in Run mode,code with data processing....45running from RAM.... .Table 16.Maximum current consumption in Sleep mode, code running from Flash or RAM.....47Table 17..48TypicalandmaximumcurrentconsumptionsinStopandStandbymodesTable 18.Typical currentconsumption inRunmode,codewithdataprocessing...51runningfromFlash........Table 19.Typical currentconsumptioninSleepmode,coderunningfromFlashor....52RAM......53Table 20.Peripheralcurrentconsumption.54Table 21.High-speedexternaluserclockcharacteristics..55Table 22.Low-speedexternaluserclockcharacteristics.56Table23.HSE4-16MHzoscillatorcharacteristics.Table 24.LSE oscillator characteristics (fsE= 32.768 kHz)......57.58Table 25.HSIoscillatorcharacteristics.Table 26.....59LSloscillatorcharacteristics.59Table 27.Low-powermodewakeuptimingsTable 28.PLLcharacteristics.....60.60Table 29.Flashmemorycharacteristics.Table 30..61Flash memory endurance and data retention. ....62Table31.Asynchronousnon-multiplexedSRAM/PSRAM/NORreadtimings.63Table 32.Asynchronousnon-multiplexedSRAM/PSRAM/NORwritetimings.64Table 33.AsynchronousmultiplexedPSRAM/NORreadtimings..Table 34..65AsynchronousmultiplexedPSRAM/NORwritetimings67Table 35.SynchronousmultiplexedNOR/PSRAMreadtimings..69Table 36.SynchronousmultiplexedPSRAMwritetimings..70Table 37.Synchronous non-multiplexed NOR/PSRAM read timings....71Table 38.Synchronous non-multiplexedPSRAMwrite timings....76Table 39.SwitchingcharacteristicsforPCCard/CFreadandwritecyclesTable 40..79SwitchingcharacteristicsforNANDFlashreadandwritecycles.80Table 41.EMScharacteristicsTable 42.EMIcharacteristics..81Table 43.ESDabsolutemaximumratings...81Table 44.Electricalsensitivities.82A5/123Doc ID14611Rev7
STM32F103xC, STM32F103xD, STM32F103xE List of tables Doc ID 14611 Rev 7 5/123 List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. STM32F103xC, STM32F103xD and STM32F103xE features and peripheral counts . . . . 11 Table 3. STM32F103xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 4. High-density timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 5. High-density STM32F103xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 6. FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 7. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 8. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 9. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 10. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 11. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 12. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 13. Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 14. Maximum current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 15. Maximum current consumption in Run mode, code with data processing running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 16. Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 47 Table 17. Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 48 Table 18. Typical current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 19. Typical current consumption in Sleep mode, coderunning from Flash or RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 20. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 21. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 22. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 23. HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 24. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 25. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 26. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 27. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 28. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 29. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 30. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . 62 Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . 63 Table 33. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 34. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 35. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 36. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 37. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 38. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 39. Switching characteristics for PC Card/CF read and write cycles . . . . . . . . . . . . . . . . . . . . 76 Table 40. Switching characteristics for NAND Flash read and write cycles . . . . . . . . . . . . . . . . . . . . 79 Table 41. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 42. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 43. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 44. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
ListoftablesSTM32F103xC,STM32F103xD,STM32F103xE...82Table 45.1/Ostaticcharacteristics.....84Table 46.OutputvoltagecharacteristicsTable 47.O AC characteristics......85...86Table 48.NRSTpincharacteristicsTable 49.TIMx characteristics..87ccharacteristics.....88Table 50.Table 51.SCL frequency (fpCLK1= 36 MHz.,VDD = 3.3 V).89SPIcharacteristics....90Table 52.Table 53.scharacteristics..93Table 54.SD/MMCcharacteristics.96.96Table 55.USBstartuptime....97Table 56.USBDCelectrical characteristics.....Table 57.USB:full-speedelectricalcharacteristics.97..98Table 58.ADCcharacteristicsTable 59..99RAIN max for fADC = 14 MHz. . :..99Table 60.ADCaccuracy-limitedtestconditionsTable 61.ADCaccuracy100...103Table 62.DACcharacteristicsTable 63.TScharacteristics.105Table 64.LFBGA144-144-ball lowprofile finepitch ball grid array,10x10mm,.1070.8 mm pitch,packagedata..Table 65.LFBGA100-10x10mmlowprofile finepitchball grid arraypackage....108mechanicaldata.Table 66.WLCSP,64-ball4.466×4.395mm,0.500mmpitch,wafer-levelchip-scale....109packagemechanicaldata...Table 67.LQFP144,20x20mm,144-pinlow-profilequadflatpackagemechanicaldata111..Table 68.LQPF100 - 14 x 14 mm 100-pin low-profile quad flat package mechanical data. .. .... 112Table 69.LQFP64-10x10mm64pinlow-profilequadflatpackagemechanicaldata....113Table 70.Package thermalcharacteristics...114Table 71.Ordering information scheme........117S6/123Doc ID14611Rev7
List of tables STM32F103xC, STM32F103xD, STM32F103xE 6/123 Doc ID 14611 Rev 7 Table 45. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 46. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 47. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 48. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 49. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 50. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 51. SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 52. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 53. I2S characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 54. SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 55. USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 56. USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Table 57. USB: full-speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Table 58. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 59. RAIN max for fADC = 14 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 60. ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 61. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table 62. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Table 63. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 64. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table 65. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 66. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 67. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 111 Table 68. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . 112 Table 69. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data. . . . . . . . . 113 Table 70. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 71. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
STM32F103xC,STM32F103xD,STM32F103xEList of figuresList of figuresFigure 1.STM32F103xC,STM32F103xD and STM32F103xEperformance line block diagram..12Figure 2.Clocktree..13Figure3.STM32F103xCandSTM32F103xEperformancelineBGA144ballout.24...25Figure 4.STM32F103xCandSTM32F103xEperformancelineBGA100balloutFigure 5..26STM32F103xCandSTM32F103xEperformancelineLQFP144pinout..Figure 6....27STM32F103xCandSTM32F103xEperformancelineLQFP100pinout....Figure7.STM32F103xCandSTM32F103xEperformanceline.28LQFP64pinout.Figure 8.STM32F103xCandSTM32F103xEperformanceline.29WLCSP64ballout,ballside..38Figure 9.Memorymap....Figure10..39Pinloadingconditions.Figure 11..39Pin inputvoltage....40Figure 12.Powersupplyscheme.Figure 13..40CurrentconsumptionmeasurementschemeFigure 14.TypicalcurrentconsumptioninRunmodeversusfrequency(at3.6V).46codewithdataprocessingrunningfromRAM,peripheralsenabled.Figure15.TypicalcurrentconsumptioninRunmodeversusfrequency(at3.6V)codewithdataprocessingrunningfromRAM,peripheralsdisabled...46Figure 16.Typical current consumption on VBAT with RTC on vs. temperature at different VBAT....48values..Figure 17.Typicalcurrent consumption in Stop mode with regulatorin runmode.49versus temperature at different Vpp values ....Figure 18.TypicalcurrentconsumptioninStopmodewithregulatorinlow-power.49modeversus temperatureat different Vpp values.Figure 19.Typical currentconsumption inStandbymodeversustemperatureat.50differentVppvaluesFigure 20...55High-speedexternalclocksourceACtimingdiagram..56Figure 21.Low-speed external clock source AC timing diagram....57Figure 22.Typicalapplicationwithan8MHzcrystal.Figure23..58Typicalapplicationwitha32.768kHzcrystal.Figure 24..62Asynchronousnon-multiplexedSRAM/PSRAM/NORreadwaveforms.63Figure 25.Asynchronousnon-multiplexedSRAM/PSRAM/NORwritewaveformsFigure 26.Asynchronous multiplexed PSRAM/NOR read waveforms..64....65Figure 27.AsynchronousmultiplexedPSRAM/NORwritewaveforms.66Figure 28.SynchronousmultiplexedNOR/PSRAMreadtimings.68Figure 29.Synchronousmultiplexed PSRAM write timings.Figure 30.Synchronousnon-multiplexedNOR/PSRAMreadtimings..70Figure 31.Synchronousnon-multiplexedPSRAMwritetimings..71Figure 32.Pc Card/CompactFlash controller waveforms for common memory read access......72Figure 33.PCCard/CompactFlashcontrollerwaveformsforcommonmemorywriteaccess......73Figure 34.PCCard/CompactFlashcontrollerwaveformsforattributememory read.74access...Figure 35.PCCard/CompactFlashcontrollerwaveformsforattributememorywrite.75access..Figure 36.PCCard/CompactFlashcontrollerwaveformsforIVOspacereadaccess.75Figure 37.PC Card/CompactFlash controller waveforms for I/O space write access.:.76NANDcontrollerwaveformsforreadaccess..78Figure38.ST7/123DocID14611Rev7
STM32F103xC, STM32F103xD, STM32F103xE List of figures Doc ID 14611 Rev 7 7/123 List of figures Figure 1. STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram . . . 12 Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 3. STM32F103xC and STM32F103xE performance line BGA144 ballout . . . . . . . . . . . . . . . 24 Figure 4. STM32F103xC and STM32F103xE performance line BGA100 ballout . . . . . . . . . . . . . . . 25 Figure 5. STM32F103xC and STM32F103xE performance line LQFP144 pinout. . . . . . . . . . . . . . . 26 Figure 6. STM32F103xC and STM32F103xE performance line LQFP100 pinout. . . . . . . . . . . . . . . 27 Figure 7. STM32F103xC and STM32F103xE performance line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 8. STM32F103xC and STM32F103xE performance line WLCSP64 ballout, ball side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 9. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 10. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 11. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 12. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 13. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) - code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 46 Figure 15. Typical current consumption in Run mode versus frequency (at 3.6 V) - code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 46 Figure 16. Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 17. Typical current consumption in Stop mode with regulator in run mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 18. Typical current consumption in Stop mode with regulator in low-power mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 19. Typical current consumption in Standby mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 20. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 21. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 22. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 23. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 24. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . . 62 Figure 25. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . . 63 Figure 26. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 27. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 28. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 29. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 30. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 31. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Figure 32. PC Card/CompactFlash controller waveforms for common memory read access . . . . . . . 72 Figure 33. PC Card/CompactFlash controller waveforms for common memory write access. . . . . . . 73 Figure 34. PC Card/CompactFlash controller waveforms for attribute memory read access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 35. PC Card/CompactFlash controller waveforms for attribute memory write access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 36. PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . . 75 Figure 37. PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . . 76 Figure 38. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
ListoffiguresSTM32F103xC,STM32F103xD,STM32F103xE.78Figure39.NANDcontrollerwaveformsforwriteaccess..Figure 40.NANDcontrollerwaveformsforcommonmemoryreadaccess.78Figure 41.NANDcontrollerwaveformsforcommonmemorywriteaccess.79..86Figure 42.I/OACcharacteristicsdefinition..86Figure 43.RecommendedNRSTpinprotectionFigure 44.cbusACwaveformsandmeasurementcircuit..89.91Figure 45.SPItimingdiagram-slavemodeandCPHA=0SPI timing diagram - slave mode and CPHA = 1(i)...91Figure 46.SPI timing diagram -master mode(1).92Figure 47.I2s slave timing diagram (Philips protocol)(1).94Figure 48.Figure 49.Ps master timing diagram (Philips protocol)(1).94SDIOhigh-speedmode.95Figure 50.....95Figure 51.SD default mode..97Figure 52.USBtimings:definitionofdata signal riseandfall timeFigure 53.ADCaccuracycharacteristics.100Figure54...101TypicalconnectiondiagramusingtheADCFigure 55.Power supply and reference decoupling (VREF+ not connected to VpDA).101Figure56.Power supply and reference decoupling (VREF+connected to VpDA)..102:104Figure 57.12-bitbuffered/non-bufferedDAC.Figure 58..106RecommendedPCBdesignrules(0.80/0.75mmpitchBGA)Figure 59.LFBGA144 - 144-ball low profile fine pitch ball grid array,10 x 10 mm,0.8 mm pitch,package outline.........107Figure 60.LFBGA100-10x10mmlowprofile finepitchballgridarraypackage...108outline..Figure 61.WLcSP,64-ball4.466x4.395mm,0.500mmpitch,wafer-levelchip-scale..109package outline...Figure 62..110RecommendedPCBdesignrules(0.5mmpitchBGA)Figure 63.LQFP144,20x20mm,144-pinlow-profilequad.111flat package outline.Recommendedfootprint(1)Figure 64..111.112Figure 65.LQFP100,14x14mm100-pinlow-profilequadflatpackageoutlineRecommendedfootprint(1)..112Figure 66.113Figure 67.LQFP64-10x10mm64pinlow-profilequadflatpackageoutlineRecommended footprint(1)Figure 68.113116Figure 69.LQFP100Ppmaxvs.TAS8/123DocID14611Rev7
List of figures STM32F103xC, STM32F103xD, STM32F103xE 8/123 Doc ID 14611 Rev 7 Figure 39. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Figure 40. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . . 78 Figure 41. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . . 79 Figure 42. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 43. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 44. I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Figure 45. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Figure 46. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Figure 47. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Figure 48. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Figure 49. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Figure 50. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Figure 51. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Figure 52. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Figure 53. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Figure 54. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Figure 55. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 101 Figure 56. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 102 Figure 57. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Figure 58. Recommended PCB design rules (0.80/0.75 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . 106 Figure 59. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Figure 60. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Figure 61. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Figure 62. Recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Figure 63. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Figure 64. Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Figure 65. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 112 Figure 66. Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Figure 67. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 113 Figure 68. Recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Figure 69. LQFP100 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
STM32F103xC,STM32F103xD,STM32F103xEIntroduction1IntroductionThisdatasheetprovidestheorderinginformationandmechanicaldevicecharacteristicsottheSTM32F103xC,STM32F103xDandSTM32F103xEhigh-densityperformancelinemicrocontrollers.FormoredetailsonthewholeSTMicroelectronicsSTM32F103xxfamilyplease refer to Section 2.2:Full compatibility throughout the family.Thehigh-densitySTM32F103xxdatasheetshouldbereadinconjunctionwiththeSTM32F10xxxreferencemanual.For information on programming,erasing and protectionofthe internal Flashmemoryplease refer to the STM32F10xxx Flash programmingmanual.ThereferenceandFlashprogrammingmanualsarebothavailablefromtheSTMicroelectronicswebsitewww.st.comForinformationontheCortexTM-M3corepleaserefertotheCortexTm-M3TechnicalReferenceManual,availablefromthewww.arm.comwebsiteatthefollowingaddress:http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddio337el.1■ECortexVUARM:IntelligentProcessorsbyARMA9/123Doc ID14611Rev7
STM32F103xC, STM32F103xD, STM32F103xE Introduction Doc ID 14611 Rev 7 9/123 1 Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F103xC, STM32F103xD and STM32F103xE high-density performance line microcontrollers. For more details on the whole STMicroelectronics STM32F103xx family, please refer to Section 2.2: Full compatibility throughout the family. The high-density STM32F103xx datasheet should be read in conjunction with the STM32F10xxx reference manual. For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F10xxx Flash programming manual. The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/
DescriptionSTM32F103xC,STM32F103xD,STM32F103xE2DescriptionTheSTM32F103xC,STM32F103xDandSTM32F103xEperformancelinefamilyincorporates the high-performance ARMCortexTm-M332-bit RISC core operating ata72MHzfrequency,high-speedembeddedmemories(Flashmemoryupto512KbytesandSRAMupto64Kbytes),andanextensiverangeofenhancedI/Osandperipheralsconnected to twoAPBbuses.Alldevicesofferthree 12-bit ADCs,fourgeneral-purpose16-bit timers plus two PwM timers,as well as standard and advanced communicationinterfaces:uptotwoICs,threeSPls,two2Ss,oneSDIO,fiveUSARTs,anUSBandaCAN.TheSTM32F103xxhigh-densityperformancelinefamilyoperates inthe-40to+105Ctemperaturerange, from a 2.0 to3.6Vpower supply.Acomprehensive set of power-savingmodeallowsthedesignoflow-powerapplications.TheSTM32F103xxhigh-densityperformance linefamilyoffersdevices insixdifferentpackagetypes:from64pins to144pins.Dependingon thedevicechosen,different setsofperipherals are included,thedescriptionbelow gives an overviewof thecompleterangeofperipheralsproposedinthisfamilyThesefeaturesmaketheSTM32F103xxhigh-densityperformance linemicrocontrollerfamily suitablefora widerange ofapplications:.Motordriveandapplicationcontrol.MedicalandhandheldequipmentPCperipheralsgamingandGPSplatforms.Industrialapplications,PLC,inverters,printers,andscannersSAlarmsystems,videointercom,andHVACOFigure1showsthegeneralblockdiagramof thedevicefamily.S10/123Doc ID14611Rev7
Description STM32F103xC, STM32F103xD, STM32F103xE 10/123 Doc ID 14611 Rev 7 2 Description The STM32F103xC, STM32F103xD and STM32F103xE performance line family incorporates the high-performance ARM® Cortex™-M3 32-bit RISC core operating at a 72 MHz frequency, high-speed embedded memories (Flash memory up to 512 Kbytes and SRAM up to 64 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All devices offer three 12-bit ADCs, four general-purpose 16- bit timers plus two PWM timers, as well as standard and advanced communication interfaces: up to two I2Cs, three SPIs, two I2Ss, one SDIO, five USARTs, an USB and a CAN. The STM32F103xx high-density performance line family operates in the –40 to +105 °C temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications. The STM32F103xx high-density performance line family offers devices in six different package types: from 64 pins to 144 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. These features make the STM32F103xx high-density performance line microcontroller family suitable for a wide range of applications: ● Motor drive and application control ● Medical and handheld equipment ● PC peripherals gaming and GPS platforms ● Industrial applications, PLC, inverters, printers, and scanners ● Alarm systems, video intercom, and HVAC Figure 1 shows the general block diagram of the device family