《微机技术与仪器系统设计》课程教学资源（芯片手册）27C040-EPROM-存储器芯片.pdf_大学文库

7 www.fairchildsemi.com FM27C040 Rev. A FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM Functional Description DEVICE OPERATION The six modes of operation of the EPROM are listed in Table 1. It should be noted that all inputs for the six modes are at TTL levels. The power supplies required are VCC and VPP. The VPP power supply must be at 12.75V during the three programming modes, and must be at 5V in the other three modes. The VCC power supply must be at 6.25V during the three programming modes, and at 5V in the other three modes. Read Mode The EPROM has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (CE/PGM) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay from CE to output (tCE). Data is available at the outputs tOE after the falling edge of OE, assuming that CE/PGM has been low and addresses have been stable for at least tACC -tOE. Standby Mode The EPROM has a standby mode which reduces the active power dissipation by over 99%, from of 65 mW to 0.55 mW. The EPROM is placed in the standby mode by applying a CMOS high signal to the CE/PGM input. When in standby mode, the outputs are in a high impedance state, independent of the OE input. Output Disable The EPROM is placed in output disable by applying a TTL high signal to the OE input. When in output disable all circuitry is enabled, except the outputs are in a high impedance state (TRISTATE). Output OR-Typing Because the EPROM is usually used in larger memory arrays, Fairchild has provided a 2-line control function that accommodates this use of multiple memory connections. The 2-line control function allows for: 1. the lowest possible memory power dissipation, and 2. complete assurance that output bus contention will not occur. To most efficiently use these two control lines, it is recommended that CE/PGM be decoded and used as the primary device selecting function, while OE be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device. Programming CAUTION: Exceeding 14V on pin 1 (VPP) will damage the EPROM. Initially, and after each erasure, all bits of the EPROM are in the “1’s” state. Data is introduced by selectively programming “0’s” into the desired bit locations. Although only “0’s” will be programmed, both “1’s” and “0’s” can be presented in the data word. The only way to change a “0” to a “1” is by ultraviolet light erasure. The EPROM is in the programming mode when the VPP power supply is at 12.75V and OE is at VIH. It is required that at least a 0.1 µF capacitor be placed across VPP, VCC to ground to suppress spurious voltage transients which may damage the device. The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. When the address and data are stable, an active low, TTL program pulse is applied to the CE/PGM input. A program pulse must be applied at each address location to be programmed. The EPROM is programmed with the Turbo Programming Algorithm shown in Figure 1. Each Address is programmed with a series of 50 µs pulses until it verifies good, up to a maximum of 10 pulses. Most memory cells will program with a single 50 µs pulse. (The standard National Semiconductor Algorithm may also be used but it will have longer programming time.) The EPROM must not be programmed with a DC signal applied to the CE/PGM input. Programming multiple EPROM in parallel with the same data can be easily accomplished due to the simplicity of the pro-gramming requirements. Like inputs of the parallel EPROM may be connected together when they are programmed with the same data. A low level TTL pulse applied to the CE/PGM input programs the paralleled EPROM. Program Inhibit Programming multiple EPROMs in parallel with different data is also easily accomplished. Except for CE/PGM all like in-puts (including OE) of the parallel EPROMs may be com-mon. A TTL low level program pulse applied to an EPROM’s CE/PGM input with VPP at 12.75V will program that EPROM. A TTL high level CE/ PGM input inhibits the other EPROMs from being programmed. Program Verify A verify should be performed on the programmed bits to determine whether they were correctly programmed. The verify may be performed with VPP at 12.75V. VPP must be at VCC, except during programming and program verify. AFTER PROGRAMMING Opaque labels should be placed over the EPROM window to prevent unintentional erasure. Covering the window will also prevent temporary functional failure due to the generation of photo currents. MANUFACTURER’S IDENTIFICATION CODE The EPROM has a manufacturer’s identification code to aid in programming. When the device is inserted in an EPROM programmer socket, the programmer reads the code and then automatically calls up the specific programming algorithm for the part. This automatic programming control is only possible with programmers which have the capability of reading the code. The Manufacturer’s Identification code, shown in Table 2, specifically identifies the manufacturer and device type. The code for FM27C040 is “8F08”, where “8F” designates that it is made by Fairchild Semiconductor, and “08” designates a 4 Megabit (512K x 8) part. The code is accessed by applying 12V ±0.5V to address pin A9. Addresses A1–A8, A10–A18, and all control pins are held at VIL. Address pin A0 is held at VIL for the manufacturer’s code, and held at VIH for the device code. The code is read on the eight data pins, O0 –O7 . Proper code access is only guaranteed at 25°C ± 5°C

8 www.fairchildsemi.com FM27C040 Rev. A FM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM Functional Description (Continued) ERASURE CHARACTERISTICS The erasure characteristics of the device are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms (Å). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000Å–4000Å range. The recommended erasure procedure for the EPROM is exposure to short wave ultraviolet light which has a wavelength of 2537Å. The integrated dose (i.e., UV intensity X exposure time) for erasure should be minimum of 15W-sec/cm2. The EPROM should be placed within 1 inch of the lamp tubes during erasure. Some lamps have a filter on their tubes which should be removed before erasure. An erasure system should be calibrated periodically. The distance from lamp to device should be maintained at one inch. The erasure time increase as the square of the distance from the lamp. (If distance is doubled the erasure time increases by factor of 4.) Lamps lose intensity as they age. When a lamp is changed, the distance has changed, or the lamp has aged, the system should be checked to make certain full erasure is occurring. Incomplete erasure will cause symptoms that can be misleading. Programmers, components, and even system designs have been erroneously suspected when incomplete erasure was the problem. SYSTEM CONSIDERATION The power switching characteristics of EPROMs require careful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the system designer: the standby current level, the active current level, and the transient current peaks that are produced by voltage transitions on input pins. The magnitude of these transient current peaks is dependent of the output capacitance loading of the device. The associated VCC transient voltage peaks can be suppressed by properly selected decoupling capacitors. It is recommended that at least a 0.1 µF ceramic capacitor be used on every device between VCC and GND. This should be a high frequency capacitor of low inherent inductance. In addition, at least a 4.7 µF bulk electrolytic capacitor should be used between VCC and GND for each eight devices. The bulk capacitor should be located near where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of the PC board traces. Mode Selection The modes of operation of the FM27C040 are listed in Table 1. A single 5V power supply is required in the read mode. All inputs are TTL levels except for VPP and A9 for device signature. TABLE 1. Modes Selection Pins CE/PGM OE VPP VCC Outputs Mode Read VIL VIL X 5.0V DOUT (Note 15) Output Disable X VIH X 5.0V High Z Standby VIH X X 5.0V High Z Programming VIL VIH 12.75V 6.25V DIN Program Verify X VIL 12.75V 6.25V DOUT Program Inhibit VIH VIH 12.75V 6.25V High Z Note 15: X can be VIL or VIH TABLE 2. Manufacturer’s Identification Code Pins A0 A9 O7 O6 O5 O4 O3 O2 O1 O0 Hex (12) (26) (21) (20) (19) (18) (17) (15) (14) (13) Data Manufacturer Code VIL 12V 1 0 0 0 1 1 1 1 8F Device Code VIH 12V 0 0 0 0 1 0 0 0 08