《微机技术与仪器系统设计》课程教学资源（芯片手册）Intel-8259A-可编程中断控制器芯片

intel. 8259A PROGRAMMABLE INTERRUPT CONTROLLER (8259A/8259A-2) Eight-Level Pri Expandable to 64 Levels ■Available in EXPRESS Programmable Interrupt Modes -Extende Temperature ange Individual Request Mask Capability Tpea2taseerad8smpemaeea2i8onareal8neyoe8agnara2msevepnoyner 231400-2 aure 2.Pin Figure 1.Block Diagram Order Number-00

December 1988 Order Number: 231468-003 8259A PROGRAMMABLE INTERRUPT CONTROLLER (8259A/8259A-2) Y 8086, 8088 Compatible Y MCS-80, MCS-85 Compatible Y Eight-Level Priority Controller Y Expandable to 64 Levels Y Programmable Interrupt Modes Y Individual Request Mask Capability Y Single a5V Supply (No Clocks) Y Available in 28-Pin DIP and 28-Lead PLCC Package (See Packaging Spec., Order Ý231369) Y Available in EXPRESS Ð Standard Temperature Range Ð Extended Temperature Range The Intel 8259A Programmable Interrupt Controller handles up to eight vectored priority interrupts for the CPU. It is cascadable for up to 64 vectored priority interrupts without additional circuitry. It is packaged in a 28-pin DIP, uses NMOS technology and requires a single a5V supply. Circuitry is static, requiring no clock input. The 8259A is designed to minimize the software and real time overhead in handling multi-level priority inter￾rupts. It has several modes, permitting optimization for a variety of system requirements. The 8259A is fully upward compatible with the Intel 8259. Software originally written for the 8259 will operate the 8259A in all 8259 equivalent modes (MCS-80/85, Non-Buffered, Edge Triggered). 231468 –1 Figure 1. Block Diagram DIP 231468 –2 PLCC 231468 –31 Figure 2. Pin Configurations

8259A intel. Table 1.Pin Description Symbol Pin No. Type Name and Function SUPPLY:+5V Supply GND GROUND cs ween W丽 wRmEiAern0mtp0cSs1owenabesthe8259Aoacap EA68nS8 D7-D0 4-11 1/o .status and interrupt-vector CAS-CAS 12,13.15 1/o SP/EN 16 INT 0 ceu's in upt pir Ro-IRz -25 JESTS: t NTA 20 Ao 27 he CPL edesa s th 2

8259A Table 1. Pin Description Symbol Pin No. Type Name and Function VCC 28 I SUPPLY: a5V Supply. GND 14 I GROUND CS 1 I CHIP SELECT: A low on this pin enables RD and WR communication between the CPU and the 8259A. INTA functions are independent of CS. WR 2 I WRITE: A low on this pin when CS is low enables the 8259A to accept command words from the CPU. RD 3 I READ: A low on this pin when CS is low enables the 8259A to release status onto the data bus for the CPU. D7–D0 4 –11 I/O BIDIRECTIONAL DATA BUS: Control, status and interrupt-vector information is transferred via this bus. CAS0–CAS2 12, 13, 15 I/O CASCADE LINES: The CAS lines form a private 8259A bus to control a multiple 8259A structure. These pins are outputs for a master 8259A and inputs for a slave 8259A. SP/EN 16 I/O SLAVE PROGRAM/ENABLE BUFFER: This is a dual function pin. When in the Buffered Mode it can be used as an output to control buffer transceivers (EN). When not in the buffered mode it is used as an input to designate a master (SP e 1) or slave (SP e 0). INT 17 O INTERRUPT: This pin goes high whenever a valid interrupt request is asserted. It is used to interrupt the CPU, thus it is connected to the CPU’s interrupt pin. IR0–IR7 18 –25 I INTERRUPT REQUESTS: Asynchronous inputs. An interrupt request is executed by raising an IR input (low to high), and holding it high until it is acknowledged (Edge Triggered Mode), or just by a high level on an IR input (Level Triggered Mode). INTA 26 I INTERRUPT ACKNOWLEDGE: This pin is used to enable 8259A interrupt-vector data onto the data bus by a sequence of interrupt acknowledge pulses issued by the CPU. A0 27 I AO ADDRESS LINE: This pin acts in conjunction with the CS, WR, and RD pins. It is used by the 8259A to decipher various Command Words the CPU writes and status the CPU wishes to read. It is typically connected to the CPU A0 address line (A1 for 8086, 8088). 2

intel. 8259A FUNCTIONAL DESCRIPTION Interrupts in Microcomputer Systems The most com method of servicing such devic or must tes et icing.It is ea ng the ula be one Figure 3a.Polled Method this Flgure 3b.Interrupt Method he n

8259A FUNCTIONAL DESCRIPTION Interrupts in Microcomputer Systems Microcomputer system design requires that I.O de￾vices such as keyboards, displays, sensors and oth￾er components receive servicing in a an efficient manner so that large amounts of the total system tasks can be assumed by the microcomputer with little or no effect on throughput. The most common method of servicing such devic￾es is the Polled approach. This is where the proces￾sor must test each device in sequence and in effect ‘‘ask’’ each one if it needs servicing. It is easy to see that a large portion of the main program is looping through this continuous polling cycle and that such a method would have a serious detrimental effect on system throughput, thus limiting the tasks that could be assumed by the microcomputer and reducing the cost effectiveness of using such devices. A more desirable method would be one that would allow the microprocessor to be executing its main program and only stop to service peripheral devices when it is told to do so by the device itself. In effect, the method would provide an external asynchronous input that would inform the processor that it should complete whatever instruction that is currently being executed and fetch a new routine that will service the requesting device. Once this servicing is com￾plete, however, the processor would resume exactly where it left off. This method is called Interrupt. It is easy to see that system throughput would drastically increase, and thus more tasks could be assumed by the micro￾computer to further enhance its cost effectiveness. The Programmable Interrupt Controller (PIC) func￾tions as an overall manager in an Interrupt-Driven system environment. It accepts requests from the peripheral equipment, determines which of the in￾coming requests is of the highest importance (priori￾ty), ascertains whether the incoming request has a higher priority value than the level currently being serviced, and issues an interrupt to the CPU based on this determination. Each peripheral device or structure usually has a special program or ‘‘routine’’ that is associated with its specific functional or operational requirements; this is referred to as a ‘‘service routine’’. The PIC, after issuing an Interrupt to the CPU, must somehow input information into the CPU that can ‘‘point’’ the Program Counter to the service routine associated with the requesting device. This ‘‘pointer’’ is an ad￾dress in a vectoring table and will often be referred to, in this document, as vectoring data. 231468 –3 Figure 3a. Polled Method 231468 –4 Figure 3b. Interrupt Method 3

8259A intel. 8259A is a de INTA (INTERRUPT ACKNOWLEDGE) ot d to DATA BUS BUFFER ens th he Data Bus Butfer. IN SERVICEREOISTETER(RR)AND READ/WRITE CONTROL LOGIC The function of this block is to accept OUTput co The inter hand The PRIORITY RESOLVER CS(CHIP SELECT) Tiiho9ttlo*Teeoneiheamoate3et地sb the bit of the WR (WRITE INTERRUPT MASK REGISTER (IMR) a90wm8wga8ewben8P58me6on RD (READ) INT (INTERRUPT) Ao 4

8259A The 8259A is a device specifically designed for use in real time, interrupt driven microcomputer systems. It manages eight levels or requests and has built-in features for expandability to other 8259A’s (up to 64 levels). It is programmed by the system’s software as an I/O peripheral. A selection of priority modes is available to the programmer so that the manner in which the requests are processed by the 8259A can be configured to match his system requirements. The priority modes can be changed or reconfigured dynamically at any time during the main program. This means that the complete interrupt structure can be defined as required, based on the total system environment. INTERRUPT REQUEST REGISTER (IRR) AND IN-SERVICE REGISTER (ISR) The interrupts at the IR input lines are handled by two registers in cascade, the Interrupt Request Reg￾ister (IRR) and the In-Service (ISR). The IRR is used to store all the interrupt levels which are requesting service; and the ISR is used to store all the interrupt levels which are being serviced. PRIORITY RESOLVER This logic block determines the priorites of the bits set in the IRR. The highest priority is selected and strobed into the corresponding bit of the ISR during INTA pulse. INTERRUPT MASK REGISTER (IMR) The IMR stores the bits which mask the interrupt lines to be masked. The IMR operates on the IRR. Masking of a higher priority input will not affect the interrupt request lines of lower quality. INT (INTERRUPT) This output goes directly to the CPU interrupt input. The VOH level on this line is designed to be fully compatible with the 8080A, 8085A and 8086 input levels. INTA (INTERRUPT ACKNOWLEDGE) INTA pulses will cause the 8259A to release vector￾ing information onto the data bus. The format of this data depends on the system mode (mPM) of the 8259A. DATA BUS BUFFER This 3-state, bidirectional 8-bit buffer is used to inter￾face the 8259A to the system Data Bus. Control words and status information are transferred through the Data Bus Buffer. READ/WRITE CONTROL LOGIC The function of this block is to accept OUTput com￾mands from the CPU. It contains the Initialization Command Word (ICW) registers and Operation Command Word (OCW) registers which store the various control formats for device operation. This function block also allows the status of the 8259A to be transferred onto the Data Bus. CS (CHIP SELECT) A LOW on this input enables the 8259A. No reading or writing of the chip will occur unless the device is selected. WR (WRITE) A LOW on this input enables the CPU to write con￾trol words (ICWs and OCWs) to the 8259A. RD (READ) A LOW on this input enables the 8259A to send the status of the Interrupt Request Register (IRR), In Service Register (ISR), the Interrupt Mask Register (IMR), or the Interrupt level onto the Data Bus. A0 This input signal is used in conjunction with WR and RD signals to write commands into the various com￾mand registers, as well as reading the various status registers of the chip. This line can be tied directly to one of the address lines. 4

intel. 8259A RAS REG CAS 1 CAS2+ INTERNAL BUS 231468-5 Figure 4a.8259A Block Diagram | 5

8259A 231468 –5 Figure 4a. 8259A Block Diagram 5

8259A intel. INTA 0r, CONTROL LOGIC NTERNAL BUS 23146 Figure 4b.8259A Block Diagram

8259A 231468 –6 Figure 4b. 8259A Block Diagram 6

intel. 8259A THE CASCADE BUFFER/COMPARATOR dat hersghr o the the e the CPU group.the INTERRUPT SEQUENCE 5.The 8 he s ence o aemsoearasoorsnanMcSe/lsse 一 If no interrup 3.h INT and rosponds When the 8259A two IN ot ng a s group em s is re 7

8259A THE CASCADE BUFFER/COMPARATOR This function block stores and compares the IDs of all 8259A’s used in the system. The associated three I/O pins (CAS0-2) are outputs when the 8259A is used as a master and are inputs when the 8259A is used as a slave. As a master, the 8259A sends the ID of the interrupting slave device onto the CAS0 –2 lines. The slave thus selected will send its preprogrammed subroutine address onto the Data Bus during the next one or two consecutive INTA pulses. (See section ‘‘Cascading the 8259A’’.) INTERRUPT SEQUENCE The powerful features of the 8259A in a microcom￾puter system are its programmability and the inter￾rupt routine addressing capability. The latter allows direct or indirect jumping to the specific interrupt rou￾tine requested without any polling of the interrupting devices. The normal sequence of events during an interrupt depends on the type of CPU being used. The events occur as follows in an MCS-80/85 sys￾tem: 1. One or more of the INTERRUPT REQUEST lines (IR7 –0) are raised high, setting the correspond￾ing IRR bit(s). 2. The 8259A evaluates these requests, and sends an INT to the CPU, if appropriate. 3. The CPU acknowledges the INT and responds with an INTA pulse. 4. Upon receiving an INTA from the CPU group, the highest priority ISR bit is set, and the correspond￾ing IRR bit is reset. The 8259A will also release a CALL instruction code (11001101) onto the 8-bit Data Bus through its D7 –0 pins. 5. This CALL instruction will initiate two more INTA pulses to be sent to the 8259A from the CPU group. 6. These two INTA pulses allow the 8259A to re￾lease its preprogrammed subroutine address onto the Data Bus. The lower 8-bit address is re￾leased at the first INTA pulse and the higher 8-bit address is released at the second INTA pulse. 7. This completes the 3-byte CALL instruction re￾leased by the 8259A. In the AEOI mode the ISR bit is reset at the end of the third INTA pulse. Otherwise, the ISR bit remains set until an appro￾priate EOI command is issued at the end of the interrupt sequence. The events occuring in an 8086 system are the same until step 4. 4. Upon receiving an INTA from the CPU group, the highest priority ISR bit is set and the correspond￾ing IRR bit is reset. The 8259A does not drive the Data Bus during this cycle. 5. The 8086 will initiate a second INTA pulse. Dur￾ing this pulse, the 8259A releases an 8-bit pointer onto the Data Bus where it is read by the CPU. 6. This completes the interrupt cycle. In the AEOI mode the ISR bit is reset at the end of the sec￾ond INTA pulse. Otherwise, the ISR bit remains set until an appropriate EOI command is issued at the end of the interrupt subroutine. If no interrupt request is present at step 4 of either sequence (i.e., the request was too short in duration) the 8259A will issue an interrupt level 7. Both the vectoring bytes and the CAS lines will look like an interrupt level 7 was requested. When the 8259A PIC receives an interrupt, INT be￾comes active and an interrupt acknowledge cycle is started. If a higher priority interrupt occurs between the two INTA pulses, the INT line goes inactive im￾mediately after the second INTA pulse. After an un￾specified amount of time the INT line is activated again to signify the higher priority interrupt waiting for service. This inactive time is not specified and can vary between parts. The designer should be aware of this consideration when designing a sys￾tem which uses the 8259A. It is recommended that proper asynchronous design techniques be fol￾lowed. 7

8259A intel. CONTROL LOGIC CAS I CA52 INTERNAL BUS 2314-7 Figure 4c.825 Block Diagram INTERRUPT SEQUENCE OUTPUTS MCS-80,MCS-85 CALL CODE hTE有U7 3146-8 grammed,while AAs are au

8259A 231468 –7 Figure 4c. 8259A Block Diagram 231468 –8 Figure 5. 8259A Interface to Standard System Bus INTERRUPT SEQUENCE OUTPUTS MCS-80, MCS-85 This sequence is timed by three INTA pulses. During the first INTA pulse the CALL opcode is enabled onto the data bus. Content of First Interrupt Vector Byte D7 D6 D5 D4 D3 D2 D1 D0 CALL CODE 1 1 0 0 1 1 0 1 During the second INTA pulse the lower address of the appropriate service routine is enabled onto the data bus. When Interval e 4 bits A5–A7 are pro￾grammed, while A0–A4 are automatically inserted by the 8259A. When Interval e 8 only A6 and A7 are programmed, while A0–A5 are automatically insert￾ed. 8

intel. 8259A Content of Second Interrupt Vector Byte IR D7 D6 D5 D4 D3 D2 D1 D0 7A7A6 10 0 6A7.A6 D7 D5 D3 D2 D1 o 1R7 11 IR6 T7 T6 T5 T4 T3 1 10 IR5 T7 T6 T5 T4 T3 10 1 1R4 2 0 0 T6T5T4T3100 183T7 T6 T5 T4 T30 11 1A7 A6 A5 0 0 0 0A7A6A50.0000 I2T7T6T5T4T3010 I1T7T6T5T4T3001 R Interval =8 I0T7T6T5T4T3000 D7 D6 D5 D4 D3 D2 D1 7A7A61 00 0 PROGRAMMING THE 8259A 6A7A61 0000 5A7A6 4 A7 2 A 0 A6 0 Operation Command Words (OCWs):Thes a.Fully nested mode A15A14A13A12A11A10A9A8 her9Gonbewnieninohe8250Aanynme 8086,8088 W哈ZATION COMMAND WORDS AL General Whene er a command is issued with Ao =0 and D4 on

8259A Content of Second Interrupt Vector Byte IR Interval e 4 D7 D6 D5 D4 D3 D2 D1 D0 7 A7 A6 A5 1 1 1 0 0 6 A7 A6 A5 1 1 0 0 0 5 A7 A6 A5 1 0 1 0 0 4 A7 A6 A5 1 0 0 0 0 3 A7 A6 A5 0 1 1 0 0 2 A7 A6 A5 0 1 0 0 0 1 A7 A6 A5 0 0 1 0 0 0 A7 A6 A5 0 0 0 0 0 IR Interval e 8 D7 D6 D5 D4 D3 D2 D1 D0 7 A7 A6 1 1 1 0 0 0 6 A7 A6 1 1 0 0 0 0 5 A7 A6 1 0 1 0 0 0 4 A7 A6 1 0 0 0 0 0 3 A7 A6 0 1 1 0 0 0 2 A7 A6 0 1 0 0 0 0 1 A7 A6 0 0 1 0 0 0 0 A7 A6 0 0 0 0 0 0 During the third INTA pulse the higher address of the appropriate service routine, which was programmed as byte 2 of the initialization sequence (A8–A15), is enabled onto the bus. Content of Third Interrupt Vector Byte D7 D6 D5 D4 D3 D2 D1 D0 A15 A14 A13 A12 A11 A10 A9 A8 8086, 8088 8086 mode is similar to MCS-80 mode except that only two Interrupt Acknowledge cycles are issued by the processor and no CALL opcode is sent to the processor. The first interrupt acknowledge cycle is similar to that of MCS-80, 85 systems in that the 8259A uses it to internally freeze the state of the interrupts for priority resolution and as a master it issues the interrupt code on the cascade lines at the end of the INTA pulse. On this first cycle it does not issue any data to the processor and leaves its data bus buffers disabled. On the second interrupt ac￾knowledge cycle in 8086 mode the master (or slave if so programmed) will send a byte of data to the processor with the acknowledged interrupt code composed as follows (note the state of the ADI mode control is ignored and A5–A11 are unused in 8086 mode): Content of Interrupt Vector Byte for 8086 System Mode D7 D6 D5 D4 D3 D2 D1 D0 IR7 T7 T6 T5 T4 T3 1 1 1 IR6 T7 T6 T5 T4 T3 1 1 0 IR5 T7 T6 T5 T4 T3 1 0 1 IR4 T7 T6 T5 T4 T3 1 0 0 IR3 T7 T6 T5 T4 T3 0 1 1 IR2 T7 T6 T5 T4 T3 0 1 0 IR1 T7 T6 T5 T4 T3 0 0 1 IR0 T7 T6 T5 T4 T3 0 0 0 PROGRAMMING THE 8259A The 8259A accepts two types of command words generated by the CPU: 1. Initialization Command Words (ICWs): Before normal operation can begin, each 8259A in the system must be brought to a starting pointÐby a sequence of 2 to 4 bytes timed by WR pulses. 2. Operation Command Words (OCWs): These are the command words which command the 8259A to operate in various interrupt modes. These modes are: a. Fully nested mode b. Rotating priority mode c. Special mask mode d. Polled mode The OCWs can be written into the 8259A anytime after initialization. INITIALIZATION COMMAND WORDS (ICWS) General Whenever a command is issued with A0 e 0 and D4 e 1, this is interpreted as Initialization Command Word 1 (ICW1). ICW1 starts the intiitalization se￾quence during which the following automatically oc￾cur. a. The edge sense circuit is reset, which means that following initialization, an interrupt request (IR) in￾put must make a low-to-high transistion to gener￾ate an interrupt. 9

8259A intel. b.The Interrupt Mask Register is cleared. esGdns,lgtaeha8ats6aveegsta Moderdnd nce (for M aaenodOwhbe Command Words 1and 2 YES (SNGL -0 A sets the 0C40 LTIM: ADE: n erval ICW4 C4: 6 n腰o。eoa1M INTEARUPALOUEST 23146 Initialization Command Word 3(ICW3) Figure6.Initialization Sequence 2gAmhr1omneahaneoena

8259A b. The Interrupt Mask Register is cleared. c. IR7 input is assigned priority 7. d. The slave mode address is set to 7. e. Special Mask Mode is cleared and Status Read is set to IRR. f. If IC4 e 0, then all functions selected in ICW4 are set to zero. (Non-Buffered mode*, no Auto￾EOI, MCS-80, 85 system). *NOTE: Master/Slave in ICW4 is only used in the buffered mode. Initialization Command Words 1 and 2 (ICW1, ICW2) A5–A15: Page starting address of service routines. In an MCS 80/85 system, the 8 request levels will generate CALLs to 8 locations equally spaced in memory. These can be programmed to be spaced at intervals of 4 or 8 memory locations, thus the 8 rou￾tines will occupy a page of 32 or 64 bytes, respec￾tively. The address format is 2 bytes long (A0–A15). When the routine interval is 4, A0–A4 are automatically in￾serted by the 8259A, while A5–A15 are programmed externally. When the routine interval is 8, A0–A5 are automatically inserted by the 8259A, while A6–A15 are programmed externally. The 8-byte interval will maintain compatibility with current software, while the 4-byte interval is best for a compact jump table. In an 8086 system A15–A11 are inserted in the five most significant bits of the vectoring byte and the 8259A sets the three least significant bits according to the interrupt level. A10–A5 are ignored and ADI (Address interval) has no effect. LTIM: If LTIM e 1, then the 8259A will operate in the level interrupt mode. Edge detect logic on the interrupt inputs will be disabled. ADI: CALL address interval. ADI e 1 then inter￾val e 4; ADI e 0 then interval e 8. SNGL: Single. Means that this is the only 8259A in the system. If SNGL e 1 no ICW3 will be issued. IC4: If this bit is setÐICW4 has to be read. If ICW4 is not needed, set IC4 e 0. Initialization Command Word 3 (ICW3) This word is read only when there is more than one 8259A in the system and cascading is used, in which case SNGL e 0. It will load the 8-bit slave register. The functions of this register are: a. In the master mode (either when SP e 1, or in buffered mode when M/S e 1 in ICW4) a ‘‘1’’ is set for each slave in the system. The master then will release byte 1 of the call sequence (for MCS- 80/85 system) and will enable the corresponding slave to release bytes 2 and 3 (for 8086 only byte 2) through the cascade lines. b. In the slave mode (either when SP e 0, or if BUF e 1 and M/S e 0 in ICW4) bits 2 –0 identify the slave. The slave compares its cascade input with these bits and, if they are equal, bytes 2 and 3 of the call sequence (or just byte 2 for 8086) are released by it on the Data Bus. 231468 –9 Figure 6. Initialization Sequence 10