intel. 8255A/8255A-5 PROGRAMMABLE PERIPHERAL INTERFACE MCS-85TM Compatible 8255A-5 24 Programmable 1/0 Pins ·8aeoptpoanetaayEasng Completely TTL Compatible Reduces System Package Count Fully Compatible with intel Improved DC Driving Capablity Microprocessor Familles ■Available in EXPRESS Improved Timing Characteristics 二2 moy Tmprure an3e ■40 Pin DIP Package eagetoaentoe2uoaot, ode (MODE 0).ea roup may be or outpu .0 iomthoohergroupriorhaRunac whichs9gines9or6adr8ctonabus.ad"5ins6oong2oe 255A Figure 2.Pin Configuration 231306- Figure 1.8255A Block Diagram 3-100 Order um www.chipdocs.com Be sure to visit ChipDocs web site or more information
intel. 8255A/8255A-5 8255A FUNCTIONAL DESCRIPTION CUnsnig8oiSCgteecnisdpsun.sues General The 8255A is a prog (cs) mmebepsopheacoieae copnseiee6。AbanrComhg25gAgmanateUhe (RD) sary to interlace peripheral devices or structures. Data Bus Buffer (W丽 otna8iem8onaroasoansterod wmbia1acotohonastno0oa8e2gsecPuo 3 (Ao and A1) Read/Write and Control Logic PagaeoctLRciodPanthastahWenpRcg Conr Staluworuom oheleasdggeantbg0reheaoeasbgrt and A1). 自 231308-3 Figure 3.8255A Block Diagram Showing Data Bus Buffer and Read/Write Control Logic Functions 3-101 www.chipdocs.com Be sure to visit ChipDocs web site for more information
intel. 8255A/8255A-5 8255A BASIC OPERATION ration (READ) 000 0 Port A Data Bus sociated ports. 01010PotB→Data Bus 1 00 1 0 Portc Data Bus Control Group A-Port A and Port C upper (C7-C4) Control Group B-Port B and Port C lower(C3-CO) Output Operation (WRITE) 00100 Data Bus→PortA allowed 01100 Data Bus→PotE 10100 Data Bus→PortC Ports A,B,and C 1110 Data Bus→Control Disable Function xxxX 1 Data Bus3-State 1101 llegal Condition enhance the power and flexibility of the 8255A. x×110 Data Bus→3-State u ach/bufferandn (RESET) 8ae。Bnaactee/ouotach/buierand Port C.One 8-bit data output latch/buffer and one for is por Group A and Group B Controls ontrol.Each port co 4-bit latchand The functional configuration of each port is pro- c8ntrarworgcoaansniorm h ie 3-102 www.chipdocs.com Be sure to visit ChipDocs web site or more information
intel. 8255A/8255A-5 -自 自 231308-4 Flgure 4.8225A Block Dlagram Sh ing Group A and Group B Control Functions Pin Names Pin Configuration D7-D0 Data Bus(Bi-Directional) RESET Reset Input Chip Select 万 Read input Write Input A0.A1 Port Address PA7-PAO Port A(BIT) PB7-PBO Port B(BIT) PC7-PCO Port C(BIT) Vcc +5 Volts GND 0 Volts 8255A OPERATIONAL DESCRIPTION 231308-5 Mode Selection 3-103 www.chipdocs.com Be sure to visit ChipDocs
intel. 8255A/8255A-5 Mode 0-Basic Input/Output Mode 1-Strobed Input/Output o,o.a D.o D,o a Mode 2-Bi-Directional Bus ereset input goes"highl be in thee will be e input r ode 25amema8eg mode 热品 ns.All of GOPA tailored" itor y com nterrupt-driven basis ORESS BUS NTROL BUS 231308-7 Figure 6.Mode Definition Format 变聚聚 e comch anaMecearet9gsgnsO99 d ls 套细细袋 aa8mea - 袋四变 Single Bit Set/Reset Feature 231308-6 Any of the eight bits of Port C can be Set or Reset Figure 5.Basic Mode Definitions and Bus cations 3-104 www.chipdocs.com Be sure to visit ChipDoc web site ormore infomation
intel. 8255A/8255A-5 CONTROL WORD INTE flip-flop definition: (BIT-SET)-INTE is set-Interrupt enable (BIT-RESET)-INTE is RESET-Interrupt disable aocalo mode selec RCTIVEEFAG Operating Modes 231308-B MODE 0(Basic Input/Output).This functional con- Figure 7.Bit Set/Reset Format psoeasmpywmen10cr7a8h6h9g 3 ports. ModeBasic Functional Defintions .Two 8-bit ports and two 4-bit port Interrupt Control Functions Any port can be input or output Outputs are latched When the 8255A is programmed to operate in mode puts are not latched 38giofnth8agouputconiguraionsarepos- MODE O(BASIC INPUT) RO 231308-9 3105 www.chipdocs.com Be sure to visit ChipDocs web site for more information
intel. 8255A/8255A-5 MODE 0(BASIC OUTPUT) 231308-10 MODE O PORT DEFINITION A Group A Group B 0, D3 00 PortA ortC Port B PortC (Upper) (Lower) 0 0 0 0 OUTPUT OUTPUT 0 OUTPUT OUTPUT 0 0 0 OUTPUT OUTPUT OUTPUT INPUT 0 0 0 OUTPUT OUTPUT 2 INPUT OUTPUT 0 0 OUTPUT OUTPUT 3 INPUT NPUT 0 1 0 0 OUTPUT INPUT 4 OUTPUT OUTPUT 0 OUTPUT INPUT 5 OUTPUT INPUT 0 OUTPUT INPUT 6 INPUT OUTPUT 0 OUTPUT INPUT 7 INPUT INPUT 0 INPUT OUTPUT 8 OUTPUT OUTPUT 1 0 0 INPUT OUTPUT 9 OUTPUT INPUT 0 INPUT OUTPUT 10 INPUT OUTPUT 1 0 INPUT OUTPUT 11 INPUT INPUT 0 0 INPUT INPUT 12 OUTPUT OUTPUT 0 INPUT INPUT 13 OUTPUT INPUT 0 INPUT INPUT 14 INPUT OUTPUT INPUT INPUT 15 INPUT INPUT 3-106 www.chipdocs.com Be sure to visit ChipDocs web site or more information
intel. 8255A/8255A-5 MODE CONFIGURATIONS 0404g020 。a 1oo o oo -D。 PC PC 231308-11 231308-12 品的 品的 3 PB,PB 231308-13 231308-14 TROL WORD 4 品品品品 品时 PAy PA PA,-PA PC,PC 231308-1 3107 www.chipdocs.com esure to visit ChipDocs web site or more
inte. 8255A/8255A-5 CONTROL WORD CONTROL WORD DD.D. 00000006 4 陀，C 231308-17 23130g-18 OL WORD 6 0,0,0,04p20,a 。 。1o 255A 255 —PC,PC PC:-PC D,Do -PC,PCo 231308-9 23t308-20 D.D.D.D.D.D.D. 时 -PC,PC 231306-22 3-108 www.chipdocs.com Be sure to visit ChipDocs web site or more information
intel. 8255A/8255A-5 o00 o -PAz-PAo 255 231308-23 231306-24 ROL WORD #13 ONTROL WORD 15 ▣ 3 255 231308-25 231308-26 Operating Modes Input Control Signal Definition MODE 1 (Strobed Input/Output).This functional p8caep091rcon8eoNM8 IBF(Input Buffer Full F/F) Mode 1 Basic Functional Definitions: input latch: n es Two Groups(Group A and Group B) -dataortad and is reset by the rising the RD input INTR(Interrupt Request) ‘gtsbPcauwogoronoansasowte 3-109 .chipdocs.com esure to visit ChipDocs web site or more