NTCONDUCTOR TECHNICAL DATA Octal 3-State Noninverting MC54/74HC244A Buffer/Line Driver/ Line Receiver J SUFFIX CE High-Performance Silicon-Gate CMOS CASE732-03 npatible with LSTTL outputs The HC24isimilar in function to the HC240A and HC241A. utputs Directly Int e ·Low Input Current:1A ◆ DT SUF :henNoeneimSRaacetcc6eMOpeiee CASE 948E-02 No. ined by JEDEC Standar RDERIN Chip Complexity:136 FETs or 34 Equivalent Gates 74HCXXXAN LOGIC DIAGRAM A12 18Y PIN ASSIGNMENT 16 ENABLEA D1 Y 19门ENABLEB 14 YA3 YE43 181YA1 A24 7l4 12 ·Y 、 N 9 21 13B2 3.15 Y819 5 GND 10 111B1 B4 17 FUNCTION TABLE Pw0S品 Outputs YA YB high impedance 2/97 REV7 MMOTOROLA
SEMICONDUCTOR TECHNICAL DATA Motorola, Inc. 1997 1 REV 7 2/97 ! ! ! High–Performance Silicon–Gate CMOS The MC54/74HC244A is identical in pinout to the LS244. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This octal noninverting buffer/line driver/line receiver is designed to be used with 3–state memory address drivers, clock drivers, and other bus–oriented systems. The device has noninverting outputs and two active–low output enables. The HC244A is similar in function to the HC240A and HC241A. • Output Drive Capability: 15 LSTTL Loads • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2 to 6 V • Low Input Current: 1 µA • High Noise Immunity Characteristic of CMOS Devices • In Compliance with the Requirements Defined by JEDEC Standard No. 7A • Chip Complexity: 136 FETs or 34 Equivalent Gates LOGIC DIAGRAM DATA INPUTS A1 A2 A3 A4 B1 B2 B3 B4 17 15 13 11 8 6 4 2 18 16 14 12 9 7 5 3 YB4 YB3 YB2 YB1 YA4 YA3 YA2 YA1 NONINVERTING OUTPUTS PIN 20 = VCC PIN 10 = GND OUTPUT ENABLES ENABLE A ENABLE B 1 19 PIN ASSIGNMENT A3 A2 YB4 A1 ENABLE A GND YB1 A4 YB2 YB3 5 4 3 2 1 10 9 8 7 6 14 15 16 17 18 19 20 11 12 13 YA2 B4 YA1 ENABLE B VCC B1 YA4 B2 YA3 B3 FUNCTION TABLE Inputs Outputs Enable A, Enable B A, B YA, YB LLL LHH HXZ Z = high impedance DW SUFFIX SOIC PACKAGE CASE 751D–04 N SUFFIX PLASTIC PACKAGE CASE 738–03 ORDERING INFORMATION MC54HCXXXAJ MC74HCXXXAN MC74HCXXXADW MC74HCXXXASD MC74HCXXXADT Ceramic Plastic SOIC SSOP TSSOP DT SUFFIX TSSOP PACKAGE CASE 948E–02 J SUFFIX CERAMIC PACKAGE CASE 732–03 1 20 1 20 SD SUFFIX SSOP PACKAGE CASE 940C–03 1 20 1 20 1 20
MC54/74HC244A MAXIMUM RATINGS Symbol Parameter Value Unit This device contains protectior Vcc DC Supply Voltage (Referenced to GND) -0.5to+7.0 n -1.5 to Vcc+1.5 nsofa Vout DC Output Voltage(Referenced to GND) -0.5 to Vcc+0.5 lin DC Input Current.per Pin ±20 mA to this high-impedance cir lout DC Output Current per Pin +35 mA DC Supply Current.Vcc and GND Pins ±75 mA r Dissipaion nAir.Plasic 88 mW used Tstg Storage Temperature -65t0+150 260 re -10mW to125°C For high frequency or he eavy orola High-Speed CMOS Data Book (DL129/D) RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max DC Supply Voltage(Referenced to GND) 20 6.0 Vin:Vout DC Input Voltage,Output Voltage (Referenced to GND) 0 Vcc TA Operating Temperature,All Package Types -55+125 c ns DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) Gua nteed Limit Symbol Parameter 8 85C ≤125C Unit VIH a 59318 VOH Vin-VIH MOTOROLA
MC54/74HC244A MOTOROLA High–Speed CMOS Logic Data DL129 — Rev 6 2 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS* ÎÎÎ ÎÎÎ SymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Parameter ÎÎÎÎÎÎ ÎÎÎÎÎÎ Value ÎÎÎ ÎÎÎ Unit ÎÎÎ ÎÎÎVCC ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Supply Voltage (Referenced to GND) ÎÎÎÎÎÎ ÎÎÎÎÎÎ – 0.5 to + 7.0 ÎÎÎ ÎÎÎV ÎÎÎ ÎÎÎVin ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Input Voltage (Referenced to GND) ÎÎÎÎÎÎ ÎÎÎÎÎÎ – 1.5 to VCC + 1.5ÎÎÎ ÎÎÎV ÎÎÎ ÎÎÎVout ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Output Voltage (Referenced to GND) ÎÎÎÎÎÎ ÎÎÎÎÎÎ – 0.5 to VCC + 0.5ÎÎÎ ÎÎÎV ÎÎÎ ÎÎÎIin ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Input Current, per Pin ÎÎÎÎÎÎ ÎÎÎÎÎÎ ± 20 ÎÎÎ ÎÎÎ mA ÎÎÎ ÎÎÎIout ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Output Current, per Pin ÎÎÎÎÎÎ ÎÎÎÎÎÎ ± 35 ÎÎÎ ÎÎÎ mA ÎÎÎ ÎÎÎICC ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Supply Current, VCC and GND Pins ÎÎÎÎÎÎ ÎÎÎÎÎÎ ± 75 ÎÎÎ ÎÎÎ mA ÎÎÎ ÎÎÎ ÎÎÎ PD ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Power Dissipation in Still Air, Plastic or Ceramic DIP† SOIC Package† SSOP or TSSOP Package† ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ 750 500 450 ÎÎÎ ÎÎÎ ÎÎÎ mW ÎÎÎ ÎÎTstgÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ Storage Temperature Î ÎÎÎÎÎÎ ÎÎÎÎ – 65 to + 150 Î ÎÎÎ ÎÎÎ ÎC Î ÎÎÎ ÎÎÎ ÎÎÎ TL ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC, SSOP or TSSOP Package) (Ceramic DIP) ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ 260 300 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ C * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. †Derating — Plastic DIP: – 10 mW/C from 65 to 125C Ceramic DIP: – 10 mW/C from 100 to 125C SOIC Package: – 7 mW/C from 65 to 125C SSOP or TSSOP Package: – 6.1 mW/C from 65 to 125C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS ÎÎÎÎ ÎÎÎÎ Symbol ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Parameter ÎÎÎ ÎÎÎMinÎÎÎ ÎÎÎ MaxÎÎÎ ÎÎÎ Unit ÎÎÎÎ ÎÎÎÎ VCC ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Supply Voltage (Referenced to GND) ÎÎÎ ÎÎÎ2.0 ÎÎÎ ÎÎÎ6.0 ÎÎÎ ÎÎÎV ÎÎÎÎ ÎÎÎÎ Vin, Vout ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Input Voltage, Output Voltage (Referenced to GND)ÎÎÎ ÎÎÎ0 ÎÎÎ ÎÎÎ VCC ÎÎÎ ÎÎÎV ÎÎÎÎ ÎÎÎÎ TA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Operating Temperature, All Package Types ÎÎÎ ÎÎΖ 55ÎÎÎ ÎÎÎ + 125ÎÎÎ ÎÎÎ C ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tr, tf ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Input Rise and Fall Time VCC = 2.0 V (Figure 1) VCC = 4.5 V VCC = 6.0 V ÎÎÎ ÎÎÎ ÎÎÎ 0 0 0 ÎÎÎ ÎÎÎ ÎÎÎ 1000 500 400 ÎÎÎ ÎÎÎ ÎÎÎ ns DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ Guaranteed Limit ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ Symbol ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ Parameter ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ Test Conditions ÎÎÎÎ ÎÎÎ ÎÎÎÎ VCC V ÎÎÎ ÎÎÎ ÎÎÎ – 55 to 25C ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 85C ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 125C ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ Unit ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ VIH ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ Minimum High–Level Input Voltage ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ Vout = VCC – 0.1 V |Iout| 20 µA ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 2.0 3.0 4.5 6.0 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 1.5 2.1 3.15 4.2 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 1.5 2.1 3.15 4.2 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 1.5 2.1 3.15 4.2 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ V ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ VIL ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ Maximum Low–Level Input Voltage ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ Vout = 0.1 V |Iout| 20 µA ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 2.0 3.0 4.5 6.0 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 0.5 0.9 1.35 1.8 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0.5 0.9 1.35 1.8 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0.5 0.9 1.35 1.8 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ V ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ VOH ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ Minimum High–Level Output Voltage ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ Vin = VIH |Iout| 20 µA ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 2.0 4.5 6.0 ÎÎÎ ÎÎÎ ÎÎÎ 1.9 4.4 5.9 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 1.9 4.4 5.9 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 1.9 4.4 5.9 ÎÎÎ ÎÎÎ ÎÎÎ V ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ Vin = VIH |Iout| 2.4 mA |Iout| 6.0 mA |Iout| 7.8 mA ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 3.0 4.5 6.0 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 2.48 3.98 5.48 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 2.34 3.84 5.34 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 2.2 3.7 5.2 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open
MC54/74HC244A DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) Guaranteed Limit Test Conditions 5 85-C125-C Unit VOL in Maximum Input Leakage Current in VcC or GND loz Three-State Leakag 6.0 ±0.5 ±50 A AC ELECTRICAL CHARACTERISTICS (CL=50 pF.Input t=tf=6ns) Guaranteed Limit Symbol -850C ≤1250 Unit 00160 135 ns 23 照 28 卧 wgm2P9gomDebrouptEnabenArY ns 0301550 1002 r9nsonTme.ayond 0050 ns 3120 15 Cin Maximum Input Capacitance 10 10 10 Cout Hgmeresbgtpucapacanae(otpin 15 alues.s e Chapter 2 of the Motorola High Typical 25"C,Vcc 5.0 V CPD Power Dissipation Capacitance (Per Buffer) 34 de the ption:PD -CPD Vcc2f+Icc Vcc. For load considerations,see Chapter 2 of the MOTOROLA
MC54/74HC244A High–Speed CMOS Logic Data DL129 — Rev 6 3 MOTOROLA DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ Guaranteed Limit ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Unit ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 125C ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 85C ÎÎÎ ÎÎÎ ÎÎÎ – 55 to 25C ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ VCC V ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ Test Conditions ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ Parameter ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ Symbol ÎÎÎÎ ÎÎÎÎ VOL ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ Maximum Low–Level Output Voltage ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ Vin = VIL |Iout| 20 µA ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 2.0 4.5 6.0 ÎÎÎ ÎÎÎ ÎÎÎ 0.1 0.1 0.1 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0.1 0.1 0.1 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0.1 0.1 0.1 ÎÎÎ ÎÎÎ ÎÎÎ V ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ Vin = VIL |Iout| 2.4 mA |Iout| 6.0 mA |Iout| 7.8 mA ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 3.0 4.5 6.0 ÎÎÎ ÎÎÎ ÎÎÎ 0.26 0.26 0.26 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0.33 0.33 0.33 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0.4 0.4 0.4 ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ Iin ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ Maximum Input Leakage CurrentÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ Vin = VCC or GND ÎÎÎÎ ÎÎÎÎ 6.0 ÎÎÎ ÎÎα 0.1ÎÎÎÎ ÎÎÎÎ ± 1.0ÎÎÎÎ ÎÎÎÎ ± 1.0 ÎÎÎ ÎÎεA ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ IOZ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ Maximum Three–State Leakage Current ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ Output in High–Impedance State Vin = VIL or VIH Vout = VCC or GND ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 6.0 ÎÎÎÎÎ ÎÎÎ ± 0.5ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ± 5.0ÎÎÎÎ ÎÎÎ ÎÎÎÎ ± 10 ÎÎÎÎÎ ÎÎÎ µA ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ICC ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ Maximum Quiescent Supply Current (per Package) ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ Vin = VCC or GND Iout = 0 µA ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 6.0 ÎÎÎÎÎ ÎÎÎ 4.0ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 40 ÎÎÎÎ ÎÎÎ ÎÎÎÎ 160 ÎÎÎÎÎ ÎÎÎ µA NOTE: Information on typical parametric values and high frequency or heavy load considerations can be found in Chapter 2 of the Motorola High– Speed CMOS Data Book (DL129/D). AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) ÎÎÎÎ ÎÎÎÎ S bl ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ P ÎÎÎÎ ÎÎÎÎ V ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ Guaranteed Limit ÎÎÎ ÎÎÎ U i ÎÎÎÎ ÎÎÎÎ Symbol ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Parameter ÎÎÎÎ ÎÎÎÎ VCC V ÎÎÎ ÎÎÎ – 55 to 25C ÎÎÎÎ ÎÎÎÎ 85C ÎÎÎÎ ÎÎÎÎ 125C ÎÎÎ ÎÎÎÎ ÎÎÎUnit ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tPLH, tPHL ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Maximum Propagation Delay, A to YA or B to YB (Figures 1 and 3) ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 2.0 3.0 4.5 6.0 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 96 50 18 15 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 115 60 23 20 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 135 70 27 23 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tPLZ, tPHZ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Maximum Propagation Delay, Output Enable to YA or YB (Figures 2 and 4) ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 2.0 3.0 4.5 6.0 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 110 60 22 19 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 140 70 28 24 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 165 80 33 28 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tPZL, tPZH ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Maximum Propagation Delay, Output Enable to YA or YB (Figures 2 and 4) ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 2.0 3.0 4.5 6.0 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 110 60 22 19 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 140 70 28 24 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 165 80 33 28 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tTLH, tTHL ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Maximum Output Transition Time, Any Output (Figures 1 and 3) ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 2.0 3.0 4.5 6.0 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 60 23 12 10 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 75 27 15 13 ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 90 32 18 15 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns ÎÎÎÎ ÎÎÎÎ Cin ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Maximum Input Capacitance ÎÎÎÎ ÎÎÎÎ — ÎÎÎ ÎÎÎ10ÎÎÎÎ ÎÎÎÎ10 ÎÎÎÎ ÎÎÎÎ10 ÎÎÎ ÎÎÎpF ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ Cout ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Maximum Three–State Output Capacitance (Output in High–Impedance State) ÎÎÎÎ ÎÎÎ ÎÎÎÎ — ÎÎÎÎÎ ÎÎÎ 15ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 15 ÎÎÎÎ ÎÎÎ ÎÎÎÎ 15 ÎÎÎÎÎ ÎÎÎ pF NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High– Speed CMOS Data Book (DL129/D). C P Di i i C i (P B ff )* Typical @ 25°C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Buffer)* 34 pF * Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D)
MC54/74HC244A SWITCHING WAVEFORMS Vcc :50% 0% ZH IPHZ 90%-VOH OUTPUTY Figure1. Figure 2 TEST CIRCUITS TEST POINT TEST POINT OUTPUT OUTPUT CONNECT TO VCC WHEN 器 Incudes all probe and jig capacitance Figure 3.Test Circuit Figure4.Test Circuit PIN DESCRIPTIONS INPUTS app outputs assume the high impedance state. OUTPUTS CONTROLS Enable A.EnableB() Device Output enables (active-ow).When a low level is applied MOTOROLA
MC54/74HC244A MOTOROLA High–Speed CMOS Logic Data DL129 — Rev 6 4 SWITCHING WAVEFORMS Figure 1. Figure 2. VCC GND tf tr DATA INPUT A OR B OUTPUT YA OR YB 10% 50% 90% 10% 50% 90% tTLH tPLH tPHL tTHL ENABLE A OR B OUTPUT Y OUTPUT Y 50% 50% 50% 90% 10% tPZL tPLZ tPZH tPHZ VCC GND HIGH IMPEDANCE VOL VOH HIGH IMPEDANCE TEST CIRCUITS * Includes all probe and jig capacitance CL* TEST POINT DEVICE UNDER TEST OUTPUT Figure 3. Test Circuit * Includes all probe and jig capacitance CL* TEST POINT DEVICE UNDER TEST OUTPUT Figure 4. Test Circuit CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. 1 kΩ PIN DESCRIPTIONS INPUTS A1, A2, A3, A4, B1, B2, B3, B4 (Pins 2, 4, 6, 8, 11, 13, 15, 17) Data input pins. Data on these pins appear in noninverted form on the corresponding Y outputs, when the outputs are enabled. CONTROLS Enable A, Enable B (Pins 1, 19) Output enables (active–low). When a low level is applied to these pins, the outputs are enabled and the devices function as noninverting buffers. When a high level is applied, the outputs assume the high impedance state. OUTPUTS YA1, YA2, YA3, YA4, YB1, YB2, YB3, YB4 (Pins 18, 16, 14, 12, 9, 7, 5, 3) Device outputs. Depending upon the state of the output– enable pins, these outputs are either noninverting outputs or high–impedance outputs
MC54/74HC244A LOGIC DETAIL AOR VERTERS MOTOROLA
MC54/74HC244A High–Speed CMOS Logic Data DL129 — Rev 6 5 MOTOROLA LOGIC DETAIL DATA INPUT A OR B ENABLE A OR ENABLE B TO THREE OTHER A OR B INVERTERS ONE OF 8 INVERTERS YA OR YB VCC
MC54/74HC244A OUTLINE DIMENSIONS KAGE -03 TO CENTER OF LEADS WHEN ML 气 A h凸凸凸凸凸凸凸凸A CING PER ANS M 50020 D 20 PL ⊕0250010@TB@ 电0250.010@TA可 A RRRRR AND TOLERANCING PE 9 ⊕0.0100.25gB@ Φ0010025@TAB 中中4西 -18xG MOTOROLA
MC54/74HC244A MOTOROLA High–Speed CMOS Logic Data DL129 — Rev 6 6 OUTLINE DIMENSIONS J SUFFIX CERAMIC PACKAGE CASE 732–03 ISSUE E N SUFFIX PLASTIC PACKAGE CASE 738–03 ISSUE E DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D–04 ISSUE E NOTES: 1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE POSITION AT SEATING PLANE, AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSIONS A AND B INCLUDE MENISCUS. DIM MIN MAX MIN MAX MILLIMETERS INCHES A 23.88 25.15 0.940 0.990 B 6.60 7.49 0.260 0.295 C 3.81 5.08 0.150 0.200 D 0.38 0.56 0.015 0.022 F 1.40 1.65 0.055 0.065 G 2.54 BSC 0.100 BSC H 0.51 1.27 0.020 0.050 J 0.20 0.30 0.008 0.012 K 3.18 4.06 0.125 0.160 L 7.62 BSC 0.300 BSC M 0 15 0 15 N 0.25 1.02 0.010 0.040 A 20 1 10 11 B F C SEATING PLANE D H G K N J M L NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. M L J 20 PL 0.25 (0.010) M T B M DIM MIN MAX MIN MAX INCHES MILLIMETERS A 1.010 1.070 25.66 27.17 B 0.240 0.260 6.10 6.60 C 0.150 0.180 3.81 4.57 D 0.015 0.022 0.39 0.55 G 0.100 BSC 2.54 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.140 2.80 3.55 L 0.300 BSC 7.62 BSC M 0 15 0 15 N 0.020 0.040 0.51 1.01 E 0.050 0.070 1.27 1.77 1 11 10 20 –A– SEATING PLANE K N G F D 20 PL –T– 0.25 (0.010) M T A M E B C F 0.050 BSC 1.27 BSC NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. –A– –B– 20 1 11 10 0.010 (0.25) B M T A S S 20X D 0.010 (0.25) M B M 10X P J F 18X G K C –T– SEATING PLANE M R X 45 DIM MIN MAX MIN MAX MILLIMETERS INCHES A 12.65 12.95 0.499 0.510 B 7.40 7.60 0.292 0.299 C 2.35 2.65 0.093 0.104 D 0.35 0.49 0.014 0.019 F 0.50 0.90 0.020 0.035 G 1.27 BSC 0.050 BSC J 0.25 0.32 0.010 0.012 K 0.10 0.25 0.004 0.009 M 0 7 0 7 P 10.05 10.55 0.395 0.415 R 0.25 0.75 0.010 0.029
MC54/74HC244A OUTLINE DIMENSIONS PLASTIC SSOP PACKAGE 0250.010 1 BAARARARBR B DETAILE DIME BbBBUB88b6 上K N FOR REFERENG a02003@Tu⑨ -K1- SECTION N-N 078 akn DETAILE DT SUFFIX PLAS AGE CASE 948E02 ISSUE A 01500TU回 NCNG FER ANS ARRAARARA K1 2 B SECTION N-N 8888888888 0250010 SARE SHONN FO 电015000阿TU甸 DETAILE G H MOTOROLA
MC54/74HC244A High–Speed CMOS Logic Data DL129 — Rev 6 7 MOTOROLA OUTLINE DIMENSIONS DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948E–02 ISSUE A DIM A MIN MAX MIN MAX INCHES 6.60 0.260 MILLIMETERS B 4.30 4.50 0.169 0.177 C 1.20 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.27 0.37 0.011 0.015 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0 8 0 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–. ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ 1 10 20 11 PIN 1 IDENT A B –T– 0.100 (0.004) C D G H SECTION N–N K K1 J J1 N N M F –W– SEATING PLANE –V– –U– 0.10 (0.004) V M T U S S 20X REF K L 2X L/2 0.15 (0.006) T U S DETAIL E 0.25 (0.010) DETAIL E 6.40 0.252 ––– ––– 0.15 (0.006) T U S SD SUFFIX PLASTIC SSOP PACKAGE CASE 940C–03 ISSUE B 20 11 1 10 H A B F M 20X REF K 0.12 (0.005) V M T U S S L L/2 PIN 1 IDENT 0.20 (0.008) M T U S –V– –U– D C 0.076 (0.003) G –T– SEATING PLANE DETAIL E N N 0.25 (0.010) ÇÇÇ ÇÇÇ ÉÉÉ ÉÉÉ K J J1 K1 SECTION N–N DIM A MIN MAX MIN MAX INCHES 7.07 7.33 0.278 0.288 MILLIMETERS B 5.20 5.38 0.205 0.212 C 1.73 1.99 0.068 0.078 D 0.05 0.21 0.002 0.008 F 0.63 0.95 0.024 0.037 G 0.65 BSC 0.026 BSC H 0.59 0.75 0.023 0.030 J 0.09 0.20 0.003 0.008 J1 0.09 0.16 0.003 0.006 K 0.25 0.38 0.010 0.015 K1 0.25 0.33 0.010 0.013 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF K DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR INTRUSION SHALL NOT REDUCE DIMENSION K BY MORE THAN 0.07 (0.002) AT LEAST MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–. L 7.65 7.90 0.301 0.311 M 0 8 0 8 DETAIL E –W–
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