maxim integrated. DS1302 Trickle-Charge Timekeeping Chip FEATURES PIN CONFIGURATIONS Reaca8eh8apmsaeontoyotn。 河 TOP VIEW 31 x 8 Battery-Backed General-Purpose RAM serial Uo for Minimum Pin Count 2.0V to 5.5V Full Operation Uses Less than 300nA at 2.0V DIP(300mils) RAM Data Veez LI1I Vcer 8npPoroptional8Bpnsoorsutbce X1四2g7四scLK Simple 3-Wire Interface GND可4 5CE TTL-Compatible(Vec=5V) SO(208 mils/150 mils) DS1202 Compatible Laboratori (U) ORDERING INFORMATION PART TEMP RANGE PIN-PACKAGE TOP MARK* DS1302+ 0Cto+70°0 PDIP (300 mils) DS1302 DS1302N+ .40PCt0+85°C 8 PDIP (300 mils) DS1302 DS1302S+ 0℃to+70℃ 8s0208mils】 DS1302S DS1302SN+ 40Ct0+85C S0(208mis) DS13025 0S13022Nt 513022 dustrial temperature grad A+anywhere on the top mar a lead-free device UL is a registered trade iters Laboratories,Inc For pricing,delivery,and ordering information,please contact Maxim Direct at 1-888-629-4642.or visit Maxim's website at www.maximintegrated.com. REV:120208
AVAILABLE Functional Diagrams Pin Configurations appear at end of data sheet. Functional Diagrams continued at end of data sheet. UCSP is a trademark of Maxim Integrated Products, Inc. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com. DS1302 Trickle-Charge Timekeeping Chip REV: 120208 FEATURES Real-Time Clock Counts Seconds, Minutes, Hours, Date of the Month, Month, Day of the Week, and Year with Leap-Year Compensation Valid Up to 2100 31 x 8 Battery-Backed General-Purpose RAM Serial I/O for Minimum Pin Count 2.0V to 5.5V Full Operation Uses Less than 300nA at 2.0V Single-Byte or Multiple-Byte (Burst Mode) Data Transfer for Read or Write of Clock or RAM Data 8-Pin DIP or Optional 8-Pin SO for Surface Mount Simple 3-Wire Interface TTL-Compatible (VCC = 5V) Optional Industrial Temperature Range: -40°C to +85°C DS1202 Compatible Underwriters Laboratories (UL®) Recognized PIN CONFIGURATIONS ORDERING INFORMATION PART TEMP RANGE PIN-PACKAGE TOP MARK* DS1302+ 0°C to +70°C 8 PDIP (300 mils) DS1302 DS1302N+ -40°C to +85°C 8 PDIP (300 mils) DS1302 DS1302S+ 0°C to +70°C 8 SO (208 mils) DS1302S DS1302SN+ -40°C to +85°C 8 SO (208 mils) DS1302S DS1302Z+ 0°C to +70°C 8 SO (150 mils) DS1302Z DS1302ZN+ -40°C to +85°C 8 SO (150 mils) DS1302ZN +Denotes a lead-free/RoHS-compliant package. *An N anywhere on the top mark indicates an industrial temperature grade device. A + anywhere on the top mark indicates a lead-free device. UL is a registered trademark of Underwriters Laboratories, Inc. VCC1 SCLK I/O CE VCC2 X1 X2 GND 8 7 6 5 1 2 3 4 DIP (300 mils) DS1302 VCC2 X1 X2 GND VCC1 SCLK I/O CE 8 7 6 5 1 2 3 4 SO (208 mils/150 mils) DS1302 TOP VIEW
DS1302 Trickle-Charge Timekeeping Chip DETAILED DESCRIPTION The DS1302 trickle-charge timekeeping chip contains a real-time clock/calendar and 31 bytes of static RAM.It ep ame s mhe reae ours.d 12-hour format with an AM/PM indicator. g'coecto1o1eapyea17aeT8oek.peaiesRenere24i8ur8 transferred to and from the clock/RAM 1 byte at a time or in a burst of up to 31 bytes.The DS1302 is designed to operate on very low power and retain data and clock information on less than 1uw The DS1302 is the successor to the DS1202.In addition to the basic timekeeping functions of the DS1202,the Vcc1,and adbackup power supplies,programmable OPERATION shows the main elements of the serial timekeeper:shift register.control logic,oscllator,real-time clock. TYPICAL OPERATING CIRCUIT 0 CPU DS1302 GND 20f13
DS1302 Trickle-Charge Timekeeping Chip 2 of 13 DETAILED DESCRIPTION The DS1302 trickle-charge timekeeping chip contains a real-time clock/calendar and 31 bytes of static RAM. It communicates with a microprocessor via a simple serial interface. The real-time clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The end of the month date is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with an AM/PM indicator. Interfacing the DS1302 with a microprocessor is simplified by using synchronous serial communication. Only three wires are required to communicate with the clock/RAM: CE, I/O (data line), and SCLK (serial clock). Data can be transferred to and from the clock/RAM 1 byte at a time or in a burst of up to 31 bytes. The DS1302 is designed to operate on very low power and retain data and clock information on less than 1μW. The DS1302 is the successor to the DS1202. In addition to the basic timekeeping functions of the DS1202, the DS1302 has the additional features of dual power pins for primary and backup power supplies, programmable trickle charger for VCC1, and seven additional bytes of scratchpad memory. OPERATION Figure 1 shows the main elements of the serial timekeeper: shift register, control logic, oscillator, real-time clock, and RAM. TYPICAL OPERATING CIRCUIT CPU DS1302 VCC VCC2 SCLK CE GND X1 X2 VCC I/O VCC1
DS1302 Trickle-Charge Timekeeping Chip Figure 1.Block Diagram 2 DS1302 CE 31 X 8 RAM TYPICAL OPERATING CHARACTERISTICS (Vcc=3.3V.TA=+25C.unless otherwise noted.) ktys.Verst 350 30 30f13
DS1302 Trickle-Charge Timekeeping Chip 3 of 13 Figure 1. Block Diagram POWER CONTROL vCC1 vCC2 GND INPUT SHIFT REGISTERS I/O SCLK COMMAND AND CONTROL LOGIC REAL TIME CLOCK 31 X 8 RAM X2 X1 CE 1Hz CL CL DS1302 TYPICAL OPERATING CHARACTERISTICS (VCC = 3.3V, TA = +25°C, unless otherwise noted.) ICC2T vs. VCC2T 5 10 15 20 25 30 2.0 3.0 4.0 5.0 VCC2 (V) SUPPLY CURRENT (uA) ICC1T vs. VCC1T 100 150 200 250 300 350 400 2.0 3.0 4.0 5.0 VCC1 (V) SUPPLY CURRENT (nA)
DS1302 Trickle-Charge Timekeeping Chip PIN DESCRIPTION PIN NAME FUNCTION Primary Power-Supply Pin in Dual Supply Configuration.Vcc is connected to a el time and dateen strhn DS1302 2 X1 DS1302 can also be d .In this 3 X2 configuration,the X1 pin is connected to the external oscillator signal and the X2 pin is floated. 4 GND Ground Input.CE signal must be asserted high during a read or a write.This pin has an CE internal 40k(typ)pulldown resistor to ground.Note:Previous data sheet revisions referred to CE as RST.The functionality of the pin has not changed. 6 is the bidir nd SCLK Input.SCLK is used to synchronize data movement on the serial interface.This pin has an internal 40k(typ)pulldown resistor to ground. weoaarepeatannsgePcanmeBate2gcaeeateahaYenmaneow ergy source is connected to this pin.to ensure against reverse 40f13
DS1302 Trickle-Charge Timekeeping Chip 4 of 13 PIN DESCRIPTION PIN NAME FUNCTION 1 VCC2 Primary Power-Supply Pin in Dual Supply Configuration. VCC1 is connected to a backup source to maintain the time and date in the absence of primary power. The DS1302 operates from the larger of VCC1 or VCC2. When VCC2 is greater than VCC1 + 0.2V, VCC2 powers the DS1302. When VCC2 is less than VCC1, VCC1 powers the DS1302. 2 X1 3 X2 Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator is designed for operation with a crystal having a specified load capacitance of 6pF. For more information on crystal selection and crystal layout considerations, refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks. The DS1302 can also be driven by an external 32.768kHz oscillator. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated. 4 GND Ground 5 CE Input. CE signal must be asserted high during a read or a write. This pin has an internal 40kΩ (typ) pulldown resistor to ground. Note: Previous data sheet revisions referred to CE as RST. The functionality of the pin has not changed. 6 I/O Input/Push-Pull Output. The I/O pin is the bidirectional data pin for the 3-wire interface. This pin has an internal 40kΩ (typ) pulldown resistor to ground. 7 SCLK Input. SCLK is used to synchronize data movement on the serial interface. This pin has an internal 40kΩ (typ) pulldown resistor to ground. 8 VCC1 Low-Power Operation in Single Supply and Battery-Operated Systems and LowPower Battery Backup. In systems using the trickle charger, the rechargeable energy source is connected to this pin. UL recognized to ensure against reverse charging current when used with a lithium battery. Go to www.maximic.com/TechSupport/QA/ntrl.htm
DS1302 Trickle-Charge Timekeeping Chip OSCILLATOR CIRCUIT The DS1302 uses an external 32.768kHz crystal.The oscillator circuit does not require any external resistors or usually less than one second. CLOCK ACCURACY TeapeaaCoaheooksdeoenPangheeceapaeiQgtbetalaheacgiiCvacthemealchAbee error will be added by crystal frequency drift caused by temperature shifts.Exteral circuit noise coupled into the for detailed information. r to App Table 1.Crystal Specifications* PARAMETER SYMBOL MIN TYP MAX UNITS Nominal Frequency fo 32.768 kHz Series Resistance ESR .45 Load Capacitance 6 PF Figure 2.Typical PC Board Layout for Crystal LOCAL GROUND PLANE (LAYER 2) CRYSTAL D COMMAND BYTE and byte.A command byte initiates each data transfer.The MSB(bit 7)must be a 1.9ffis0.wmesloheDs1302hml6edsabledBt6speeiescockWcalendardatafiogc0orRAMdataflogc1 Figure 3.Address/Command Byte 7 0 AAA阳 50f13
DS1302 Trickle-Charge Timekeeping Chip 5 of 13 OSCILLATOR CIRCUIT The DS1302 uses an external 32.768kHz crystal. The oscillator circuit does not require any external resistors or capacitors to operate. Table 1 specifies several crystal parameters for the external crystal. Figure 1 shows a functional schematic of the oscillator circuit. If using a crystal with the specified characteristics, the startup time is usually less than one second. CLOCK ACCURACY The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional error will be added by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the oscillator circuit may result in the clock running fast. Figure 2 shows a typical PC board layout for isolating the crystal and oscillator from noise. Refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for detailed information. Table 1. Crystal Specifications* PARAMETER SYMBOL MIN TYP MAX UNITS Nominal Frequency fO 32.768 kHz Series Resistance ESR 45 kΩ Load Capacitance CL 6 pF *The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for additional specifications. Figure 2. Typical PC Board Layout for Crystal LOCAL GROUND PLANE (LAYER 2) CRYSTAL X1 X2 GND NOTE: AVOID ROUTING SIGNALS IN THE CROSSHATCHED AREA (UPPER LEFTHAND QUADRANT) OF THE PACKAGE UNLESS THERE IS A GROUND PLANE BETWEEN THE SIGNAL LINE AND THE PACKAGE. COMMAND BYTE Figure 3 shows the command byte. A command byte initiates each data transfer. The MSB (bit 7) must be a logic 1. If it is 0, writes to the DS1302 will be disabled. Bit 6 specifies clock/calendar data if logic 0 or RAM data if logic 1. Bits 1 to 5 specify the designated registers to be input or output, and the LSB (bit 0) specifies a write operation (input) if logic 0 or read operation (output) if logic 1. The command byte is always input starting with the LSB (bit 0). Figure 3. Address/Command Byte 1 RAM C K A4 A3 A2 A1 A0 RD W R 76543210
DS1302 Trickle-Charge Timekeeping Chip CE AND CLOCK CONTROL Driving the CE input high initiates all data transfers.The CE input serves two functions.First,CE turns on the 89e8e2eeecEeaaas8aenoesecndtecEs9 thenSen9ecedgegtesheacbVngda data pwe-up.C must ben Vc.0SCLK mustbehenCvestate. that in nex bit 0. DATA OUTPUT eaes8s88scKa3eshhae6ebe.a色amepe28 data b utpu loo of th of the command byte is written. stated SCLK.Data is output starting with bit 0. BURST MODE d for eit her the c ar or the RAM regis s by ad essing loc eeesnodaiaso9ge23p3oty3liocai0nsgholgh37nhecoccalearRegsiesorlocaion31n the RAM registers.Reads or writes in burst mode start with bit 0 of address 0. When writing to the clock registers in the burst mode,the first eight registers must be written in order for the data to rega byte CLOCK/CALENDAR Tgstere.9neaeamaoaenacaeoioeab2ea9heagahepapee9sereyterIbe3TetoaentbeoRTe timendcaenderreinteny-code deim()ormat spond to the day of er-defined but result in undefined operatior When reading or writing the time and date lemaln e me n date reter the uer buerre symco ndary(user)buffers are us ed to prevent errors when the internal registers ours data must be re-initialized whenever the 12/24 bit is changed. 60f13
DS1302 Trickle-Charge Timekeeping Chip 6 of 13 CE AND CLOCK CONTROL Driving the CE input high initiates all data transfers. The CE input serves two functions. First, CE turns on the control logic that allows access to the shift register for the address/command sequence. Second, the CE signal provides a method of terminating either single-byte or multiple-byte CE data transfer. A clock cycle is a sequence of a rising edge followed by a falling edge. For data inputs, data must be valid during the rising edge of the clock and data bits are output on the falling edge of clock. If the CE input is low, all data transfer terminates and the I/O pin goes to a high-impedance state. Figure 4 shows data transfer. At power-up, CE must be a logic 0 until VCC > 2.0V. Also, SCLK must be at a logic 0 when CE is driven to a logic 1 state. DATA INPUT Following the eight SCLK cycles that input a write command byte, a data byte is input on the rising edge of the next eight SCLK cycles. Additional SCLK cycles are ignored should they inadvertently occur. Data is input starting with bit 0. DATA OUTPUT Following the eight SCLK cycles that input a read command byte, a data byte is output on the falling edge of the next eight SCLK cycles. Note that the first data bit to be transmitted occurs on the first falling edge after the last bit of the command byte is written. Additional SCLK cycles retransmit the data bytes should they inadvertently occur so long as CE remains high. This operation permits continuous burst mode read capability. Also, the I/O pin is tristated upon each rising edge of SCLK. Data is output starting with bit 0. BURST MODE Burst mode can be specified for either the clock/calendar or the RAM registers by addressing location 31 decimal (address/command bits 1 through 5 = logic 1). As before, bit 6 specifies clock or RAM and bit 0 specifies read or write. There is no data storage capacity at locations 9 through 31 in the Clock/Calendar Registers or location 31 in the RAM registers. Reads or writes in burst mode start with bit 0 of address 0. When writing to the clock registers in the burst mode, the first eight registers must be written in order for the data to be transferred. However, when writing to RAM in burst mode it is not necessary to write all 31 bytes for the data to transfer. Each byte that is written to will be transferred to RAM regardless of whether all 31 bytes are written or not. CLOCK/CALENDAR The time and calendar information is obtained by reading the appropriate register bytes. Table 3 illustrates the RTC registers. The time and calendar are set or initialized by writing the appropriate register bytes. The contents of the time and calendar registers are in the binary-coded decimal (BCD) format. The day-of-week register increments at midnight. Values that correspond to the day of week are user-defined but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on.). Illogical time and date entries result in undefined operation. When reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the internal registers update. When reading the time and date registers, the user buffers are synchronized to the internal registers the rising edge of CE. The countdown chain is reset whenever the seconds register is written. Write transfers occur on the falling edge of CE. To avoid rollover issues, once the countdown chain is reset, the remaining time and date registers must be written within 1 second. The DS1302 can be run in either 12-hour or 24-hour mode. Bit 7 of the hours register is defined as the 12- or 24- hour mode-select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20–23 hours). The hours data must be re-initialized whenever the 12/24 bit is changed
DS1302 Trickle-Charge Timekeeping Chip CLOCK HALT FLAG WRITE-PROTECT BIT preensagwnieocpeaicms9Pe10Re1eg1serco'e0ntoer3nmsaitebsoieneagn,nteoreePeoeeBbd should be cleared before attempting to write to the device. TRICKLE-CHARGE REGISTER This register controls the trickle-charge characteristics of the DS1302.The simplified schematic of Figure 5 shows the basic components of the trickle charger.The trickle-charge select(TCS)bits(bits 4 to 7)control the selection of the trickle To prevent accid eony a patter 1010 enables the trckl thth charger.All othe 2 and Vme 1.If DS is 01 etween Vcc2 and Vcc1.The Table 2.Trickle Charger Resistor and Diode Select FUNCTION X X X X X X 0 0 Disabled X 0 X Disabled Disabled 0 0 1 Diode.2k 0 1 0 0 1 0 1 Diode,4kQ 0 1 0 0 1 1 1 Diode.8k2 1 0 1 0 1 0 2 Diodes.2kQ 1 0 1 0 1 0 1 2 Diodes,4kQ 0 1 0 1 0 2 Diodes.8k 10 1 1 1 0 0 Initial power-on state Assume that a system power supply of 5is applied to and a supe cap is connected to Vcct.Aiso assume hatehetrctw 8eC22eeebeealenlaheasb8medodeandresstorRibetwenveaandVecitThemamlm l=(5.0V-diode drop)/R1=(5.0V-0.7)/2k2=2.2mA creas 70f13
DS1302 Trickle-Charge Timekeeping Chip 7 of 13 CLOCK HALT FLAG Bit 7 of the seconds register is defined as the clock halt (CH) flag. When this bit is set to logic 1, the clock oscillator is stopped and the DS1302 is placed into a low-power standby mode with a current drain of less than 100nA. When this bit is written to logic 0, the clock will start. The initial power-on state is not defined. WRITE-PROTECT BIT Bit 7 of the control register is the write-protect bit. The first seven bits (bits 0 to 6) are forced to 0 and always read 0 when read. Before any write operation to the clock or RAM, bit 7 must be 0. When high, the write-protect bit prevents a write operation to any other register. The initial power-on state is not defined. Therefore, the WP bit should be cleared before attempting to write to the device. TRICKLE-CHARGE REGISTER This register controls the trickle-charge characteristics of the DS1302. The simplified schematic of Figure 5 shows the basic components of the trickle charger. The trickle-charge select (TCS) bits (bits 4 to 7) control the selection of the trickle charger. To prevent accidental enabling, only a pattern of 1010 enables the trickle charger. All other patterns will disable the trickle charger. The DS1302 powers up with the trickle charger disabled. The diode select (DS) bits (bits 2 and 3) select whether one diode or two diodes are connected between VCC2 and VCC1. If DS is 01, one diode is selected or if DS is 10, two diodes are selected. If DS is 00 or 11, the trickle charger is disabled independently of TCS. The RS bits (bits 0 and 1) select the resistor that is connected between VCC2 and VCC1. The resistor and diodes are selected by the RS and DS bits as shown in Table 2. Table 2. Trickle Charger Resistor and Diode Select TCS BIT 7 TCS BIT 6 TCS BIT 5 TCS BIT 4 DS BIT 3 DS BIT 2 RS BIT 1 RS BIT 0 FUNCTION X X X X X X 0 0 Disabled X X X X 0 0 X X Disabled X X X X 1 1 X X Disabled 1 0 1 0 0 1 0 1 1 Diode, 2kΩ 1 0 1 0 0 1 1 0 1 Diode, 4kΩ 1 0 1 0 0 1 1 1 1 Diode, 8kΩ 1 0 1 0 1 0 0 1 2 Diodes, 2kΩ 1 0 1 0 1 0 1 0 2 Diodes, 4kΩ 1 0 1 0 1 0 1 1 2 Diodes, 8kΩ 0 1 0 1 1 1 0 0 Initial power-on state Diode and resistor selection is determined by the user according to the maximum current desired for battery or super cap charging. The maximum charging current can be calculated as illustrated in the following example. Assume that a system power supply of 5V is applied to VCC2 and a super cap is connected to VCC1. Also assume that the trickle charger has been enabled with one diode and resistor R1 between VCC2 and VCC1. The maximum current IMAX would therefore be calculated as follows: IMAX = (5.0V – diode drop) / R1 ≈ (5.0V – 0.7V) / 2kΩ ≈ 2.2mA As the super cap charges, the voltage drop between VCC2 and VCC1 decreases and therefore the charge current decreases
DS1302 Trickle-Charge Timekeeping Chip CLOCK/CALENDAR BURST MODE The clock/calendar command byte sp fies burst mode operation.In this mode,the first eight clock/calendar registers can be consecutively read or written(see Table 3)starting with bit 0 of address 0. If the write- tect bit is set high when a writ e clock/calendar burst mode is specified no data transfer will occur to eightcockWcalendaregisters(thsinctudeshecontolregstel.Thetickechargerisnotac At the beginning of a clock burst read,the current time is transferred to a second set of registers.The time RAM The static RAM is 31 x 8 bytes addressed consecutively in the RAM address space. RAM BURST MODE Iead0rwmienleeT3essiagwtTo,pedeg。hthsmode,he31RaMregsterscanbeconseautivety REGISTER SUMMARY Aregister data format summary is shown in Table 3. CRYSTAL SELECTION A 32.768kHz crystal can be directly connected to the DS1302 via pins 2 and 3(X1,X2).The crystal selected for Figure 4.Data Transfer Summary SINGLE-BYTE READ CE 几几几几几几几T R/W A0 A1 A2 A3 A4 R/C 1D0 D1 D2 D3 D4 D5 DG D7 SINGLE-BYTE WRITE CE 几ΠΠΠΠΠΠΠΠΠ凡 R/W A0 A1 A2 A3 A4 R/C 1DO D1 D2 D3 D4 D5 D6 D7 NOTE:IN BURST MODE.CE IS KEPT HIGH AND ADDITIONAL SCLK CYCLES ARE SENT UNTIL THE END OF THE BURST. 80f13
DS1302 Trickle-Charge Timekeeping Chip 8 of 13 CLOCK/CALENDAR BURST MODE The clock/calendar command byte specifies burst mode operation. In this mode, the first eight clock/calendar registers can be consecutively read or written (see Table 3) starting with bit 0 of address 0. If the write-protect bit is set high when a write clock/calendar burst mode is specified, no data transfer will occur to any of the eight clock/calendar registers (this includes the control register). The trickle charger is not accessible in burst mode. At the beginning of a clock burst read, the current time is transferred to a second set of registers. The time information is read from these secondary registers, while the clock may continue to run. This eliminates the need to re-read the registers in case of an update of the main registers during a read. RAM The static RAM is 31 x 8 bytes addressed consecutively in the RAM address space. RAM BURST MODE The RAM command byte specifies burst mode operation. In this mode, the 31 RAM registers can be consecutively read or written (see Table 3) starting with bit 0 of address 0. REGISTER SUMMARY A register data format summary is shown in Table 3. CRYSTAL SELECTION A 32.768kHz crystal can be directly connected to the DS1302 via pins 2 and 3 (X1, X2). The crystal selected for use should have a specified load capacitance (CL) of 6pF. For more information on crystal selection and crystal layout consideration, refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks. Figure 4. Data Transfer Summary A1 A2 A3 A4 R/C 1 CE SCLK I/O R/W A0 D0 D1 D2 D3 D4 D5 D6 D7 SINGLE-BYTE READ A1 A2 A3 A4 R/C 1 CE SCLK I/O R/W A0 D0 D1 D2 D3 D4 D5 D6 D7 SINGLE-BYTE WRITE NOTE: IN BURST MODE, CE IS KEPT HIGH AND ADDITIONAL SCLK CYCLES ARE SENT UNTIL THE END OF THE BURST
DS1302 Trickle-Charge Timekeeping Chip Table 3.Register Address/Definition RTC READ WRITE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3BIT 2BIT 1 BIT 0 RANGE 2 CH 10 Seconds 85h 84h 121240 10 AMIPM Hour Hour 1-12/0-23 87h 86h 00 10 Date Date 1-31 89h 88h 0 0 0 Month 1-12 8Bh 8Ah 0000 0 Day 1-7 8Dh 8Ch 10 Year Year 00-99 CLOCK BURST BFh BEh RAM cih coh 00 00-FF FDh FCh 00-FFh RAM BURST FFh FEh☐ Figure 5.Programmable Trickle Charger TRICKLE CHARGE REGISTER (90h write 91h read Bit 7Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCS。,■TRICKLE CHARGER SELECT TCS3 TCS2 TCS1 TCSO DS1 DSO ROUT1 ROUTO DS.DIODE SELECT ROUT RESISTOR SELECT NOTE ONLY 1010 ENABLES CHARGER 9of13
DS1302 Trickle-Charge Timekeeping Chip 9 of 13 Table 3. Register Address/Definition RTC READ WRITE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RANGE 81h 80h CH 10 Seconds Seconds 00–59 83h 82h 10 Minutes Minutes 00–59 10 85h 84h 12/24 0 AM/PM Hour Hour 1–12/0–23 87h 86h 0 0 10 Date Date 1–31 89h 88h 0 0 0 10 Month Month 1–12 8Bh 8Ah 0 0 0 0 0 Day 1–7 8Dh 8Ch 10 Year Year 00–99 8Fh 8Eh WP 0 0 0 0 0 0 0 — 91h 90h TCS TCS TCS TCS DS DS RS RS — CLOCK BURST BFh BEh RAM C1h C0h 00-FFh C3h C2h 00-FFh C5h C4h 00-FFh . . . . . . . . . FDh FCh 00-FFh RAM BURST FFh FEh Figure 5. Programmable Trickle Charger 2K Ω 4k Ω 8k Ω R1 R3 R2 VCC2 VCC1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCS3 TCS2 TCS1 TCS0 DS1 DS0 ROUT1 ROUT0 TRICKLE CHARGE REGISTER (90h write, 91h read) 1 0F 16 SELECT NOTE: ONLY 1010b ENABLES CHARGER 1 OF 2 SELECT 1 OF 3 SELECT TCS0-3 = TRICKLE CHARGER SELECT DS0-1 = DIODE SELECT ROUT0-1 = RESISTOR SELECT
DS1302 Trickle-Charge Timekeeping Chip ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground .-0.5Vto+7.0W 0°Cto+708 ng Tempe Soldering Temperature (leads.10 seconds) .260( Soldering Temperature (surface mount). .See IPC/JEDEC J-STD-020 -40C PARamETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage Vec1.Vec2 (Notes 2.10) 2.0 3.3 5.5 V Logic 1 Input VH (Note2) 2.0 Vcc =2.0V +0.3 Logic 0 Input (Note2) -0.3 Vcc =5V -0.3 +0.8 DC ELECTRICAL CHARACTERISTICS (Ta=0°Cto+70°C or TA=-40°Cto+85°C)(Note1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Leakage (Notes 5,13) 85 500 V/O Leakage lLo (Notes5,13) 85 500 A Logic 1 Output (loH =-0.4mA) Vcc 2.0V 1.6 Vcc=5V (Note 2) Logic 1 Output (lo =-1.0mA) 2.4 Logic o Output (I=1.5mA) Vec =2.0V 04 Logic 0 Output (loL=4.0mA) Voc=5V (Note 2) 04 20N 894. 04 Vec =5V mA Vcc1=2.0V 0.3 Vcc1=5V A Standby Current(Oscillator Vcc1=2.0V 100 CH=1 Disabled) Icc1s Vcc1=5V (Notes9.11,13) 1 100 nA IND 5 200 Active Supply Current Vcc2=2.0V CH =0 0.425 (Oscillator Enabled) Vcc2=5V (Notes 4.12) mA 128 Voc2=2.0V CH =0 25.3 Vcc2 5V (Notes 3,12) 81 A Vec2 2.0V CH=1 (Notes 9.12) 36 HA Voc2=5V 80 R1 2 Trickle-Charge Resistors R2 kQ R3 8 0.7 10of13
DS1302 Trickle-Charge Timekeeping Chip 10 of 13 ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground.-0.5Vto +7.0V Operating Temperature Range, Commercial.0°C to +70°C Operating Temperature Range, Industrial (IND).-40°C to +85°C Storage Temperature Range.-55°C to +125°C Soldering Temperature (leads, 10 seconds).260°C Soldering Temperature (surface mount).See IPC/JEDEC J-STD-020 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (TA = 0°C to +70°C or TA = -40°C to +85°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage VCC1, VCC2 VCC1, VCC2 (Notes 2, 10) 2.0 3.3 5.5 V Logic 1 Input VIH (Note 2) 2.0 VCC + 0.3 V VCC = 2.0V -0.3 +0.3 Logic 0 Input VIL VCC = 5V (Note 2) -0.3 +0.8 V DC ELECTRICAL CHARACTERISTICS (TA = 0°C to +70°C or TA = -40°C to +85°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Leakage ILI (Notes 5, 13) 85 500 μA I/O Leakage ILO (Notes 5, 13) 85 500 μA Logic 1 Output (IOH = -0.4mA) VCC = 2.0V 1.6 Logic 1 Output (IOH = -1.0mA) VOH VCC = 5V (Note 2) 2.4 V Logic 0 Output (IOL = 1.5mA) VCC = 2.0V 0.4 Logic 0 Output (IOL = 4.0mA) VOL VCC = 5V (Note 2) 0.4 V Active Supply Current VCC1 = 2.0V 0.4 (Oscillator Enabled) ICC1A VCC1 = 5V CH = 0 (Notes 4, 11) 1.2 mA Timekeeping Current VCC1 = 2.0V 0.2 0.3 (Oscillator Enabled) ICC1T VCC1 = 5V CH = 0 (Notes 3, 11,13) 0.45 1 μA VCC1 = 2.0V 1 100 VCC1 = 5V 1 100 Standby Current (Oscillator Disabled) ICC1S IND CH = 1 (Notes 9, 11, 13) 5 200 nA Active Supply Current VCC2 = 2.0V 0.425 (Oscillator Enabled) ICC2A VCC2 = 5V CH = 0 (Notes 4, 12) 1.28 mA Timekeeping Current VCC2 = 2.0V 25.3 (Oscillator Enabled) ICC2T VCC2 = 5V CH = 0 (Notes 3, 12) 81 μA VCC2 = 2.0V CH = 1 (Notes 9, 12) Standby Current (Oscillator 25 Disabled) ICC2S VCC2 = 5V 80 μA R1 2 Trickle-Charge Resistors R2 4 R3 8 kΩ Trickle-Charge Diode Voltage Drop VTD 0.7 V